AM79C970A Просмотр технического описания (PDF) - Advanced Micro Devices

Номер в каталоге

Компоненты Описание

Список матч

AM79C970A

PCnet™-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product

Advanced Micro Devices 

Am79C970A

PCnet™-PCI II Single-Chip Full-Duplex Ethernet

Controller for PCI Local Bus Product

DISTINCTIVE CHARACTERISTICS

n Single-chip Ethernet controller for the

Peripheral Component Interconnect (PCI) local

bus

n Supports ISO 8802-3 (IEEE/ANSI 802.3) and

Ethernet standards

n Direct interface to the PCI local bus (Revision

2.0 compliant)

n High-performance 32-bit Bus Master

architecture with integrated DMA buffer

management unit for low CPU and bus

utilization

n Software-compatible with AMD PCnet family,

LANCE/C-LANCE, and Am79C900 ILACC

register and descriptor architecture

n Compatible with PCnet family driver software

n Full-duplex operation for increased network

bandwidth

n Big endian and little endian byte alignments

supported

n 3.3 V/5 V signaling for PCI bus interface

n Low-power CMOS design with two sleep modes

allows reduced power consumption for critical

battery-powered applications and Green PCs

n Integrated Magic Packet™ support for remote

wake up of Green PCs

n Individual 272-byte transmit and 256-byte

receive FIFOs provide frame buffering for

increased system latency and support the

following features:

— Automatic retransmission with no FIFO reload

— Automatic receive stripping and transmit

padding (individually programmable)

— Automatic runt frame rejection

— Automatic selection of received collision frames

GENERAL DESCRIPTION

The 32-bit PCnet-PCI II single-chip full-duplex Ethernet

controller is a highly integrated Ethernet system solu-

tion designed to address high-performance system ap-

plication requirements. It is a flexible bus-mastering

n Microwire EEPROM interface supports

jumperless design and provides through-chip

programming

n Supports optional Boot PROM for diskless node

applications

n Look-Ahead Packet Processing (LAPP) data

handling technique reduces system overhead

by allowing protocol analysis to begin before

end of receive frame

n Integrated Manchester encoder/decoder

n Provides integrated attachment unit interface

(AUI) and 10BASE-T transceiver with automatic

port selection

n Automatic twisted-pair receive polarity

detection and automatic correction of the

receive polarity

n Optional byte padding to long-word boundary

on receive

n Dynamic transmit FCS generation

programmable on a frame-by-frame basis

n Internal/external loopback capabilities

n Supports the following types of network

interfaces:

— AUI to external 10BASE-2, 10BASE-5,

10BASE-T, or 10BASE-F MAU

— Internal 10BASE-T transceiver with Smart

Squelch to twisted-pair medium

n JTAG Boundary Scan (IEEE 1149.1) test access

port interface and NAND Tree test mode for

board-level production connectivity test

n Supports external address detection interface

(EADI)

n 4 programmable LEDs for status indication

n 132-pin PQFP and 144-pin TQFP packages

n Support for operation in industrial temperature

range (–40°C to +85°C) available in both

packages

device that can be used in any application, including

network-ready PCs, printers, fax modems, and

bridge/router designs. The bus-master architecture

provides high data throughput in the system and low

Publication# 19436 Rev: E Amendment/0

Issue Date: June 2000

Share Link: