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AM79C970A

PCnet™-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product

Advanced Micro Devices 

PIN DESCRIPTION

PCI Interface

AD[31:0]

Address and Data

Input/Output

Address and data are multiplexed on the same bus in-

terface pins. During the first clock of a transaction

AD[31:0] contain a physical address (32 bits). During

the subsequent clocks AD[31:0] contain data. Byte or-

dering is little endian by default. AD[7:0] are defined as

least significant byte and AD[31:24] are defined as the

most significant byte. For FIFO data transfers, the PC-

net-PCI II controller can be programmed for big endian

byte ordering. See CSR3, bit 2 (BSWP) for more de-

tails.

During the address phase of the transaction, when the

PCnet-PCI II controller is a bus master, AD[31:2] will

address the active Double Word (DWord). The PC-

net-PCI II controller always drives AD[1:0] to ‘00’ during

the address phase indicating linear burst order. When

the PCnet-PCI II controller is not a bus master, the

AD[31:0] lines are continuously monitored to determine

if an address match exists for slave transfers.

During the data phase of the transaction, AD[31:0] are

driven by the PCnet-PCI II controller when performing

bus master write and slave read operations. Data on

AD[31:0] is latched by the PCnet-PCI II controller when

performing bus master read and slave write operations.

When RST is active, AD[31:0] are inputs for NAND tree

testing.

C/BE[3:0]

Bus Command and Byte Enables Input/Output

Bus command and byte enables are multiplexed on the

same bus interface pins. During the address phase of

the transaction, C/BE[3:0] define the bus command.

During the data phase C/BE[3:0] are used as byte en-

ables. The byte enables define which physical byte

lanes carry meaningful data. C/BE0 applies to byte 0

(AD[7:0]) and C/BE3 applies to byte 3 (AD[31:24]). The

function of the byte enables is independent of the byte

ordering mode (BSWP, CSR3, bit 2).

When RST is active, C/BE[3:0] are inputs for NAND

tree testing.

CLK

Clock

Input

This clock is used to drive the system bus interface and

the internal buffer management unit. All bus signals are

sampled on the rising edge of CLK and all parameters

are defined with respect to this edge. The PCnet-PCI II

controller operates over a range of 0 MHz to 33 MHz.

This clock is not used to drive the network functions.

When RST is active, CLK is an input for NAND tree

testing.

DEVSEL

Device Select

Input/Output

The PCnet-PCI II controller drives DEVSEL when it de-

tects a transaction that selects the device as a target.

The device samples DEVSEL to detect if a target

claims a transaction that the PCnet-PCI II controller

has initiated.

When RST is active, DEVSEL is an input for NAND tree

testing.

FRAME

Cycle Frame

Input/Output

FRAME is driven by the PCnet-PCI II controller when it

is the bus master to indicate the beginning and duration

of a transaction. FRAME is asserted to indicate a bus

transaction is beginning. FRAME is asserted while data

transfers continue. FRAME is deasserted before the

final data phase of a transaction. When the PCnet-PCI

II controller is in slave mode, it samples FRAME to de-

termine the address phase of transaction.

When RST is active, FRAME is an input for NAND tree

testing.

GNT

Bus Grant

Input

This signal indicates that the access to the bus has

been granted to the PCnet-PCI II controller.

The PCnet-PCI II controller supports bus parking.

When the PCI bus is idle and the system arbiter asserts

GNT without an active REQ from the PCnet-PCI II con-

troller, the device will drive the AD[31:0], C/BE[3:0] and

PAR lines.

When RST is active, GNT is an input for NAND tree

testing.

IDSEL

Initialization Device Select

Input

This signal is used as a chip select for the PCnet-PCI II

controller during configuration read and write transac-

tions.

When RST is active, IDSEL is an input for NAND tree

testing.

INTA

Interrupt Request

Input/Output

An attention signal which indicates that one or more of

the following status flags is set: BABL, EXDINT, IDON,

JAB, MERR, MISS, MFCO, MPINT, RCVCCO, RINT,

SINT, SLPINT, TINT, TXSTRT and UINT. Each status

flag has either a mask or an enable bit which allows for

suppression of INTA assertion. The flags have the fol-

lowing meaning:

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Am79C970A

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