AM79C970 Просмотр технического описания (PDF) - Advanced Micro Devices

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AM79C970

PCnet™-PCI Single-Chip Ethernet Controller for PCI Local Bus

Advanced Micro Devices 

AMD

PRELIMINARY

DETAILED FUNCTIONS

Bus Interface Unit (BIU)

The bus interface unit is built of several state machines

that run synchronously to CLK. One bus interface unit

state machine handles accesses where the PCnet-PCI

controller is the bus slave, and another handles ac-

cesses where the PCnet-PCI controller is the bus mas-

ter. All inputs are synchronously sampled. All outputs

are synchronously generated on the rising edge of CLK.

Bus Acquisition

The PCnet-PCI microcode (in the buffer management

section) will determine when a DMA transfer should be

initiated. The first step in any PCnet-PCI bus master

transfer is to acquire ownership of the bus. This task is

handled by synchronous logic within the BIU. Bus own-

ership is requested with the REQ signal and ownership

is granted by the arbiter through the GNT signal.

Figure 1 shows the PCnet-PCI controller bus acquisi-

tion. GNT is asserted at clock 3. The PCnet-PCI control-

ler starts driving AD[31:00] and C/BE[3:0] prior to clock

4. FRAME is asserted at clock 5 indicating a valid ad-

dress and command on AD[31:00] and C/BE[3:0].

ADSTEP (bit 7) in the PCI Command register is set to

ONE to indicated that the PCnet-PCI controller uses ad-

dress stepping. Address stepping in only used for the

first address phase of a bus master period.

CLK

1

2

3

4

5

FRAME

AD

ADDR

C/BE

CMD

REQ

GNT

Figure 1. Bus Acquisition

18220C-3

Note that assertion of the STOP bit in CSR0 will not

cause a deassertion of the REQ signal. Note also that a

read of the RESET register, (I/O resource at offset 14h

from the PCnet-PCI I/O base address) will not cause a

deassertion of the REQ signal. Either of these actions

will cause the internal master state machine logic to

cease operations, but the REQ signal will remain active

until the GNT signal is asserted. Following either of the

above actions, on the next clock cycle after the GNT sig-

nal is asserted, the PCnet-PCI controller will deassert

the REQ signal.

Assertion of a minimum-width pulse on the RST pin will

cause the REQ signal to deassert immediately following

the assertion of the RST pin. In this case, the PCnet-PCI

controller will not wait for the assertion of the GNT signal

before deasserting the REQ signal.

1-888

Am79C970

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