AM79C970 Просмотр технического описания (PDF) - Advanced Micro Devices

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AM79C970

PCnet™-PCI Single-Chip Ethernet Controller for PCI Local Bus

Advanced Micro Devices 

AMD

PRELIMINARY

Basic Non-Burst Write

The PCnet-PCI controller uses non-burst write cycles to

access the receive and transmit descriptor entries.

Some of the write accesses to the receive buffer mem-

ory are also in non-burst mode. All PCnet-PCI controller

non-burst write accesses are of the PCI command type

Memory Write (type 7).

Figure 5 shows two non-burst write access within one

arbitration cycle. The PCnet-PCI controller will drop

FRAME between two consecutive non-burst write cy-

cles. The PCnet-PCI controller will re-request the bus

immediately if it is preempted before starting the second

access. The example below shows an extended cycle

for the first access. The target asserts DEVSEL 2 clock

cycles after the address phase (FRAME asserted) and

adds one extra wait state by asserting TRDY only on

clock 7. The second write cycle in the example shows a

ZERO wait state access.

CLK

1

2

3

4

5

6

7

8

9

10

11

FRAME

AD

C/BE

ADDR DATA

0111 BE's

ADDR DATA

0111 BE's

PAR

PAR PAR

PAR PAR

IRDY

TRDY

DEVSEL

REQ

GNT

DEVSEL is sampled by the PCnet-PCI controller.

Figure 5. Non-Burst Write Cycles With and Without Wait States

18220C-7

1-892

Am79C970

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