AK4565 Просмотр технического описания (PDF) - Asahi Kasei Microdevices

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AK4565

Low Power 20bit CODEC with built-in ALC

Asahi Kasei Microdevices 

ASAHI KASEI

[AK4565]

Power Supply

PDN pin

PDN pin may be “L” at power-up.

ADC Internal

State

PD

4128/fs

INIT

GD

AIN

SDTO0,1

DAC Internal

State

SDTI

AOUT

Control register

“0”data

PD

GD (1)

(4)

INIT-1

INIT-2

Write to register

Read from register

External clocks

Inhibit-1 Inhibit-2

Inhibit-1

Normal

PM

GD (1)

4128/fs

INIT

Normal

GD

Normal

(2) (3) “0”data

Idle Noise

PM

(1)

Normal

GD (1)

“0”data

(4)

GD (1)

Normal

Normal

Normal

INIT-2

Normal

(5)

The clocks may be stopped.

Figure 8. Power-up/Power-down Timing Example

• INIT:

• PD:

• PM:

• INIT-1:

• INIT-2:

• Inhibit-1:

• Inhibit-2:

Initializing. At this time, STAT bit is “0”. When this flag becomes “1”, INIT process has completed.

IPGA is MUTE state.

Power-down state. ADC is output “0”, analog output of DAC goes floating.

Power-down state by operating Power Management bit

Initializing all registers.

Initializing read only registers in control registers.

Inhibits writing and reading to all control registers.

Inhibits writing to all control registers.

Note: Please refer to “explanation of register” about the condition of each register.

(1) Digital output corresponding to the analog input and analog output corresponding to the digital input are delayed

by the group delay (GD).

(2) If the analog signal does not be input, the digital outputs have the op-amp of input and some noise in ADC.

(3) ADC data is “0” data at power-down.

(4) A few noise occurs at the “↓ ↑” of PDN signal. Please mute the analog output externally if the noise influences

the system application.

(5) When the external clocks are stopped, the AK4565 should be placed in the power-down state (PDN pin = “L” or

PM3-0 bit = “0”) .

MS0132-E-01

- 12 -

2003/05

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