AK4565 Просмотр технического описания (PDF) - Asahi Kasei Microdevices

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AK4565

Low Power 20bit CODEC with built-in ALC

Asahi Kasei Microdevices 

ASAHI KASEI

[AK4565]

Addr

01H

Register Name

Power Management

R/W

Default

D7

D6

D5

D4

D3

D2

D1

D0

0

0

PM3 PM2

0

PM1

0

PM0

R/W

0

0

0

1

0

1

0

1

PM0: IPGA and ALC circuit power control.

0: Power OFF

1: Power ON (Default)

After exiting PM0 = “0”, IPGA goes default value.

PM1: ADC power control.

0: Power OFF

1: Power ON (Default)

After exiting PM1 = “0”, the initializing cycle (4128/fs) of ADC is started. Then output data of ADC becomes

“0”.

PM2: DAC power control.

0: Power OFF

1: Power ON (Default)

PM3: Used both as power control of analog loopback circuit and as selection of MUX. (0: DAC, 1: Analog loopback)

When PM3 goes “1”, input for output-AMP is selected to analog loopback circuit from DAC output. Output

MUX and AMP are powered-down when PDN = “L” or PM2 = PM3 = “0”.

The loopback output and the MUX selecting DAC output is a MIXER with the switch in practice. Therefore,

when both PM2 and PM3 select ON, the analog loopback signal and DAC output are mixed by Gain 1.

The AK4565 can be partially powered-down by ON/OFF (“1”/ “0”) of PM3-0 bits. When PDN pin goes “L”,

all the circuit in AK4565 can be powered-down regardless of PM3-0 bits.

When the AK4565 is powered-down by PM3-0 bits, contents of registers are kept. However IPGA gain is

reset when PM0 bit is “0”. (refer to “Operation of IPGA” description)

VCOM circuit is powered-down when PM bit is all “0”.

MCLK, BCLK and LRCK should not stopped except the case of PM0 = PM1 = PM2 = PM3 = “0” or PDN=

“L”.

MS0132-E-01

- 21 -

2003/05

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