ADV7533 Просмотр технического описания (PDF) - Analog Devices
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ADV7533 Datasheet PDF : 12 Pages
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ADV7533
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
BALL A1
CORNER
1
2
3
4
5
6
7
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
F6, G6
DRx3−/DRx3+
F5, G5
DRx2−/DRx2+
F4, G4
DRx1−/DRx1+
F3, G3
DRx0−/DRx0+
F2, G2
DRxC−/DRxC+
C3
PD
C5
C4
C1
C2
D3
B7, A7
A2, A1
A4, A3
A6, A5
D5
B4
D4, E3
R_EXT
HPD
SPDIF/I2S
SCLK/MCLK
LRCLK
TxC−/TxC+
Tx2−/Tx2+
Tx1−/Tx1+
Tx0−/Tx0+
INT
AVDD
V1P2
A
Tx2+
Tx2–
Tx1+
B
V3P3
GND
GND
C
SPDIF/I2S SCLK/MCLK PD
D
DDCSCL DDCSDA
LRCLK
E
GND
DVDD
V1P2
F
GND
DRxC– DRx0–
G
DVDD
DRxC+ DRx0+
Tx1–
AVDD
HPD
V1P2
DVDD
DRx1–
DRx1+
Tx0+
GND
REXT
INT
SDA
DRx2–
DRx2+
Tx0–
TxC+
GND
TxC–
PVDD
GND
CEC CECCLK
SCL
GND
DRx3–
GND
DRx3+ A2VDD
ADV7533
TOP VIEW
(BALL SIDE DOWN)
Not to Scale
Figure 4. Pin Configuration
Type1
I
I
I
I
I
I
I
I
I
I
I
O
O
O
O
O
P
P
Description
MIPI/DSI Differential Pair for Lane 3. Unused channel should be connected to ground.
MIPI/DSI Differential Pair for Lane 2. Unused channel should be connected to ground.
MIPI/DSI Differential Pair for Lane 1.
MIPI/DSI Differential Pair for Lane 0.
MIPI/DSI Differential Clock.
Power-Down. Programmable polarity is determined at power-up. The I2C address and
the PD polarity are set by the PD pin state when the supplies are applied to the
ADV7533. Internally pulled up for 1; if 0 desired, pull down to ground with a 2 kΩ
resistor. Supports typical CMOS logic levels from 1.8 V up to 3.3 V.
Sets internal reference currents. Place a 1 KΩ resistor (1% tolerance) between this pin
and ground.
Hot Plug Detect Signal. Indicates to the interface whether the receiver is connected. 1.8
V to 5.0 V CMOS logic level.
S/PDIF or I2S Audio Data Input. Represents the S/PDIF block or the two channels of
audio available through I2S. Supports typical CMOS logic levels from1.8 V to 3.3 V.
Audio Clock. Supports typical CMOS logic levels from1.8 V to 3.3 V. Unused input should
be connected to ground.
Audio Left/Right Clock Input. Supports typical CMOS logic levels from1.8 V to 3.3 V.
Unused input should be connected to ground.
Differential Clock Output. Differential clock output at pixel clock rate; TMDS logic level.
Differential Output Channel 2. Differential output of the red data at 10× the pixel clock
rate; TMDS logic level.
Differential Output Channel 1. Differential output of the green data at 10× the pixel
clock rate; TMDS logic level.
Differential Output Channel 0. Differential output of the blue data at 10× the pixel clock
rate; TMDS logic level.
Interrupt. CMOS logic level. A 2 kΩ pull-up resistor to interrupt the microcontroller I/O
supply is recommended. This is a low active signal.
1.8 V Power Supply for TMDS Outputs. Should be filtered and as quiet as possible.
Digital Logic Supply (1.2 V or 1.8 V). Set to 1.2 V for lowest power consumption. Should
be filtered and as quiet as possible.
Rev. 0 | Page 9 of 12
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