ADV7533 Просмотр технического описания (PDF) - Analog Devices
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ADV7533 Datasheet PDF : 12 Pages
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ADV7533
Parameter
AVDD
V1P2 (1.2 V)
A2VDD
PVDD
V3P3—HDMI/HDCP Memory
Transmitter Total Power
V1P2 = 1.2 V
V1P2 = 1.8 V
AC SPECIFICATIONS
TMDS Output Clock Frequency
TMDS Output Clock Duty Cycle
TMDS Differential Swing
Differential Output Timing
Low-to-High Transition Time
High-to-Low Transition Time
AUDIO AC TIMING2
SCLK Duty Cycle
When N = Even Number
When N = Odd Number
I2S, S/PDIF Setup, tASU
I2S, S/PDIF Hold Time, tAHLD
LRCLK Setup Time, tASU
LRCLK Hold Time, tAHLD
CEC
CEC_CLK Frequency3
CEC_CLK Accuracy
CEC_CLK Duty Cycle
I2C INTERFACE
SCL Clock Frequency
SDA Setup Time, tDSU
SDA Hold Time, tDHO
Setup for Start, tSTASU
Hold Time for Start, tSTAH
Setup for Stop, tSTOSU
Bus Free Between Stop and Start, tBUF
SCL High, tHIGH
SCL Low, tLOW
Conditions
HDMI analog core (24 bits at
720p)
HDMI/DSI digital core (DSI 30
bits/HDMI 24 bits at 720p)
MIPI DPHY (30 bits/three
lanes/720p)
HDMI PLL (24 bits at 720p)
HDMI HDCP memory
720p, 30-bit DSI in; 720p, 36-bit
HDMI out; typical random
pattern with CSC enabled,
HDCP enabled, audio enabled
Temp
Full
Full
Full
Full
Full
Full
Full
Test
Level1 Min
IV
IV
IV
IV
IV
IV
VI
25°C IV
20
25°C IV
48
25°C VII
800
25°C VII
75
25°C VII
75
Full IV
40
Full IV
49
Full IV
2
Full IV
2
Full IV
2
Full IV
2
Full
VIII
3
Full VIII
−2
Full
VIII
40
Full VIII
Full VIII
100
Full VIII
100
Full VIII
0.6
Full VIII
0.6
Full VIII
0.6
Full VIII
1.3
Full VIII
0.6
Full VIII
1.3
1 See the Explanation of Test Levels section.
2 12 MHz crystal for default register settings.
3 Only applies to S/PDIF if external MCLK is used.
4 I2C data rates of 100 KHz and 400 KHz are supported.
ADV7533BCBZ
Typ Max Unit
11
mA
39
mA
12
mA
11
mA
0.3
mA
120 154
mW
204
mW
112
MHz
52
%
1000 1200 mV
175
ps
175
ps
50 60
%
50 51
%
ns
ns
ns
ns
12 100
MHz
+2
%
60
%
4004
kHz
ns
ns
μs
μs
μs
μs
μs
μs
Rev. 0 | Page 5 of 12
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