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ADP3162

5-Bit Programmable 2-Phase Synchronous Buck Controller

Analog Devices 

ADP3162

Parameter

Symbol

Conditions

Min Typ

SUPPLY

DC Supply Current

Normal Mode

UVLO Mode

UVLO Threshold Voltage

UVLO Hysteresis

ICC

ICC(UVLO)

VUVLO

VCC ≤ VUVLO, VCC Rising

3.8

220

5.9 6.4

0.1 0.4

NOTES

1All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.

2Guaranteed by design, not tested in production.

Specifications subject to change without notice.

Max

5.5

400

6.9

0.6

Unit

mA

µA

V

V

ABSOLUTE MAXIMUM RATINGS*

VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +15 V

CS+, CS– . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VCC + 0.3 V

All Other Inputs and Outputs . . . . . . . . . . . . . –0.3 V to +10 V

Operating Ambient Temperature Range . . . . . . . 0°C to 70°C

Operating Junction Temperature . . . . . . . . . . . . . . . . . . 125°C

Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C

θJA

Two-Layer Board . . . . . . . . . . . . . . . . . . . . . . . . . . 125°C/W

Four-Layer Board . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

*This is a stress rating only; operation beyond these limits can cause the device to

be permanently damaged. Unless otherwise specified, all voltages are referenced

to GND.

ORDERING GUIDE

Model

Temperature Package

Range

Description

Package

Option

ADP3162JR 0°C to 70°C Narrow Body SOIC R-16A (SO-16)

PIN CONFIGURATION

VID3 1

16 VCC

VID2 2

15 REF

VID1 3

14 CS–

VID0 4 ADP3162 13 PWM1

TOP VIEW

VID25 5 (Not to Scale) 12 PWM2

COMP 6

11 CS+

FB 7

10 PWRGD

CT 8

9 GND

PIN FUNCTION DESCRIPTIONS

Pin Mnemonic Function

1–4, VID3 –VID0, Voltage Identification DAC Inputs.

5 VID25

These pins are pulled up to an internal

reference, providing a Logic 1 if left open.

The DAC output programs the FB regula-

tion voltage from 1.05 V to 1.825 V.

6 COMP

Error Amplifier Output and Compensation

Point. The voltage at this output programs

the output current control level between

CS+ and CS–.

7 FB

Feedback Input. Error amplifier input for

remote sensing of the output voltage.

8 CT

External capacitor CT connection to ground

sets the frequency of the device.

9 GND

Ground. All internal signals of the ADP3162

are referenced to this ground.

10 PWRGD

Open drain output that signals when the out-

put voltage is in the proper operating range.

11 CS+

Current Sense Positive Node. Positive input

for the current comparator. The output

current is sensed as a voltage at this pin with

respect to CS–.

12 PWM2

Logic-level output for the Phase 2 driver.

13 PWM1

Logic-level output for the Phase 1 driver.

14 CS–

Current Sense Negative Node. Negative

input for the current comparator.

15 REF

3.0 V Reference Output.

16 VCC

Supply Voltage for the ADP3162.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although

the ADP3162 features proprietary ESD protection circuitry, permanent damage may occur on

devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are

recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

REV. A

–3–

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