ADM2486BRW Просмотр технического описания (PDF) - Analog Devices
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ADM2486BRW Datasheet PDF : 20 Pages
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ADM2486
TIMING SPECIFICATIONS
2.7 V ≤ VDD1 ≤ 5.5 V, 4.75 V ≤ VDD2 ≤ 5.25 V, TA = TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
DRIVER
Maximum Data Rate
Propagation Delay, tPLH, tPHL
RTS-to-DE Propagation Delay
Pulse Width Distortion, tPWD
Switching Skew, tSKEW
Rise/Fall Time, tR, tF
Enable Time
Disable Time
Enable Skew, |tAZH − tBZL|, |tAZL − tBZH|
Disable Skew, |tAHZ − tBLZ|, |tALZ − tBHZ|
RECEIVER
Propagation Delay, tPLH, tPHL
Differential Skew, tSKEW
Enable Time
Disable Time
POWER_VALID INPUT
Enable Time
Disable Time
Min Typ Max Unit Test Conditions/Comments
20
Mbps
25
45
55
ns
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 7
20
35
55
ns
See Figure 8
5
ns
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 7 and
Figure 12
2
5
ns
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 7 and
Figure 12
5
15
ns
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 7 and
Figure 12
43
53
ns
See Figure 9 and Figure 14
43
55
ns
See Figure 9 and Figure 14
1
3
ns
See Figure 9 and Figure 14
2
5
ns
See Figure 9 and Figure 14
25
45
55
ns
CL = 15 pF, see Figure 10 and Figure 13
5
ns
CL = 15 pF, see Figure 10 and Figure 13
3
13
ns
RL = 1 kΩ, CL = 15 pF, see Figure 11 and Figure 15
3
13
ns
RL = 1 kΩ, CL = 15 pF, see Figure 11 and Figure 15
1
2
µs
3
5
µs
Rev. C | Page 5 of 20
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