ADJD-S312-CR999 Просмотр технического описания (PDF) - Avago Technologies
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ADJD-S312-CR999 Datasheet PDF : 18 Pages
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Addressing
Each slave device on the serial bus needs to have a
unique address. This is the first byte that is sent by the
master-transmitter after the START condition. The address
is defined as the first seven bits of the first byte.
The eighth bit or least significant bit (LSB) determines
the direction of data transfer. A ‘one’ in the LSB of the
first byte indicates that the master will read data from
the addressed slave (master-receiver and slave-transmit-
ter). A ‘zero’ in this position indicates that the master will
write data to the addressed slave (master-transmitter and
slave-receiver).
A device whose address matches the address sent by the
master will respond with an acknowledge for the first
byte and set itself up as a slave-transmitter or slave-re-
ceiver depending on the LSB of the first byte.
The slave address on ADJD-S312 is 0x58 (7-bits).
MSB
LSB
A6 A5 A4 A3 A2 A1 A0
R/W
1
0
1
1
0
0
0
Slave address
Figure 7: Slave Addressing
Start condition
Master will write data
Data format
ADJD-S312 uses a register-based programming architec-
ture. Each register has a unique address and controls a
specific function inside the chip.
To write to a register, the master first generates a START
condition. Then it sends the slave address for the device
it wants to communicate with. The least significant bit
(LSB) of the slave address must indicate that the master
wants to write to the slave. The addressed device will
then acknowledge the master.
The master writes the register address it wants to access
and waits for the slave to acknowledge. The master then
writes the new register data. Once the slave acknowl-
edges, the master generates a STOP condition to end the
data transfer. See figure 8.
To read from a register, the master first generates a START
condition. Then it sends the slave address for the device
it wants to communicate with. The least significant bit
(LSB) of the slave address must indicate that the master
wants to write to the slave. The addressed device will
then acknowledge the master.
The master writes the register address it wants to access
and waits for the slave to acknowledge. The master then
generates a repeated START condition and resends the
slave address sent previously. The least significant bit
(LSB) of the slave address must indicate that the master
wants to read from the slave. The addressed device will
then acknowledge the master.
The master reads the register data sent by the slave and
sends a no acknowledge signal to stop reading. The
master then generates a STOP condition to end the data
transfer. See figure 9.
Stop condition
S A6 A5 A4 A3 A2 A1 A0 W A D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 A P
Master sends
slave address
Master writes
register address
Master writes
register data
Slave acknowledge
Slave acknowledge
Slave acknowledge
Figure 8: Register Byte Write Protocol
Start condition
Master will write data
Repeated start
condition
Master will read data
Stop condition
S A6 A5 A4 A3 A2 A1 A0 W A D7 D6 D5 D4 D3 D2 D1 D0 A Sr A6 A5 A4 A3 A2 A1 A0 R A D7 D6 D5 D4 D3 D2 D1 D0 A P
Master sends
slave address
Master writes
register address
Master sends
slave address
Master reads
register data
Slave acknowledge
Slave acknowledge
Slave acknowledge
Master not
acknowledge
Figure 9: Register Byte Read Protocol
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