AD9645 Просмотр технического описания (PDF) - Analog Devices
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AD9645 Datasheet PDF : 36 Pages
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Data Sheet
AD9645
Timing Diagrams
Refer to the Memory Map Register Descriptions section and Table 20 for SPI register settings.
N–1
VINx±
N
tA
N+1
CLK–
CLK+
DDR
SDR
DCO–
DCO+
DCO–
DCO+
FCO–
BITWISE
MODE
FCO+
D0A–
D0A+
D1A–
D1A+
FCO–
BYTEWISE
MODE
FCO+
D0A–
D0A+
D1A–
D1A+
tEH
tEL
tCPD
tFCO
tPD
tFRAME
tDATA
D12 D10 D08 D06 D04 D02 LSB
0
D12 D10 D08 D06 D04 D02 LSB
0
N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16
MSB
N – 17
D11
N – 17
D09
N – 17
D07
N – 17
D05
N – 17
D03
N – 17
D01
N – 17
tLD
0
MSB
N – 17 N – 16
D11
N – 16
D09
N – 16
D07
N – 16
D05
N – 16
D03
N – 16
D01
N – 16
0
N – 16
VINx±
D05 D04 D03 D02 D01 LSB
0
0
D05 D04 D03 D02 D01 LSB
0
0
N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16
MSB D12 D11 D10 D09 D08 D07 D06 MSB D12 D11 D10 D09 D08 D07 D06
N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16
Figure 2. 16-Bit DDR/SDR, Two-Lane, 1× Frame Mode (Default)
N–1
tA
N
N+1
CLK–
CLK+
DDR
SDR
DCO+
DCO–
DCO+
DCO–
FCO–
BITWISE
MODE
FCO+
D0A–
D0A+
D1A–
D1A+
FCO–
BYTEWISE
MODE
FCO+
D0A–
D0A+
D1A–
D1A+
tEH
tEL
tFCO
tFRAME
tPD
tDATA
D10 D08 D06 D04 D02 LSB D10 D08 D06 D04 D02 LSB
N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16
MSB
N – 17
D09
N – 17
D07
N – 17
D05
N – 17
D03
N – 17
D01
N – 17
MSB
N – 16
D09
N – 16
tLD
D07 D05
N – 16 N – 16
D03
N – 16
D01
N – 16
D05 D04 D03 D02 D01 LSB D05 D04 D03 D02 D01 LSB
N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16
MSB D10 D09 D08 D07 D06 MSB D10 D09 D08 D07 D06
N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16
Figure 3. 12-Bit DDR/SDR, Two-Lane, 1× Frame Mode
Rev. B | Page 7 of 36
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