AD9645 Просмотр технического описания (PDF) - Analog Devices
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AD9645 Datasheet PDF : 36 Pages
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AD9645
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter
Electrical
AVDD to AGND
DRVDD to AGND
Digital Outputs to AGND
(D0x±, D1x±, DCO+, DCO−,
FCO+, FCO−)
CLK+, CLK− to AGND
VINx+, VINx− to AGND
SCLK/DFS, SDIO/PDWN, CSB to AGND
RBIAS to AGND
VREF to AGND
VCM to AGND
Environmental
Operating Temperature Range (Ambient)
Maximum Junction Temperature
Lead Temperature (Soldering, 10 sec)
Storage Temperature Range (Ambient)
Rating
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−40°C to +85°C
150°C
300°C
−65°C to +150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Data Sheet
THERMAL RESISTANCE
The exposed paddle is the only ground connection on the chip.
The exposed paddle must be soldered to the AGND plane of the
user’s circuit board. Soldering the exposed paddle to the user’s
board also increases the reliability of the solder joints and
maximizes the thermal capability of the package.
Table 7. Thermal Resistance
Package Type
Airflow
Velocity
(m/sec)
θ 1, 2
JA
32-Lead LFCSP, 0
37.1
5 mm × 5 mm 1.0
32.4
2.5
29.1
θ 1, 3
JC
3.1
θ 1, 4
JB
20.7
Ψ 1, 2
JT
0.3
0.5
0.8
1 Per JEDEC JESD51-7, plus JEDEC JESD51-5 2S2P test board.
2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
3 Per MIL-STD 883, Method 1012.1.
4 Per JEDEC JESD51-8 (still air).
Unit
°C/W
°C/W
°C/W
Typical θJA is specified for a 4-layer PCB with a solid ground
plane. As shown in Table 7, airflow improves heat dissipation,
which reduces θJA. In addition, metal in direct contact with the
package leads from metal traces, through holes, ground, and
power planes reduces the θJA.
ESD CAUTION
Rev. B | Page 10 of 36
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