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AD8387

700 MHz to 2700 MHz Quadrature Modulator

Analog Devices 

AD8387

FUNCTIONAL DESCRIPTION

The AD8387 is a system building block designed to directly

drive the columns of LCD microdisplays of the type popularized

for use in projection systems. It has 12 channels of precision,

12-bit DACs loaded from a dual, high speed, 12-bit wide input.

Precision current feedback amplifiers, providing well damped

pulse response and fast voltage settling into large capacitive

loads, buffer the 12 outputs. Laser trimming at the wafer level

ensures low absolute output errors and tight channel-to-channel

matching. Tight part-to-part matching in high resolution

systems is guaranteed by the use of external voltage references.

REFERENCE AND CONTROL INPUT DESCRIPTION

Data Transfer/Start Sequence Control—Input Data

Loading, Data Transfer

A valid XFR is initiated when it is held HIGH during a rising

CLK edge.

Data is transferred to the outputs and a new loading sequence is

initiated on the next rising CLK edge, immediately following a

valid XFR.

During a loading sequence, 12-bit words are loaded sequentially

into 12 internal channels.

When the AD8387 is configured for single data bus (DSW =

LOW), data is loaded on both the rising and falling edges of

CLK. When configured for dual data bus (DSW = HIGH),

data is loaded on the rising edges of CLK only.

DSW Control—Data Mode Switch

When this input is HIGH, the AD8387 is in dual data bus

mode. Data is loaded from both DBA(0:11) and DBB(0:11)

on the rising CLK edge simultaneously. R/L does not change

the active CLK edge in dual data bus mode. When LOW, the

AD8387 is in single data bus mode. Data is loaded on the rising

CLK edge from DBA(0:11) and on the falling CLK edge from

DBB(0:11) when R/L is LOW. With R/L HIGH, data is loaded

on the falling CLK edge from DBA(0:11) and on the rising CLK

edge from DBB(0:11).

Right/Left Control—Input Data Loading

To facilitate image mirroring, the direction of the loading

sequence is set by the R/L control. A new loading sequence

begins at Channel 0 and proceeds to Channel 11 when the R/L

control is held LOW. It begins at Channel 11 and proceeds to

Channel 0 when the R/L control is held HIGH.

TSW Control—Thermal Switch Control

When this input is HIGH, the thermal switch is enabled. When

LOW or left unconnected, the thermal switch is disabled.

An internal, 10 kΩ pull-down resistor disables the thermal

switch when this pin is left unconnected.

GSW Control—Output Mode Switch

When this input is HIGH, the video outputs operate normally.

When LOW or left open, the video outputs are forced to

AGND. This function operates when AVCC power is off but

requires DVCC power to be on.

INV Control and ISW Control—Analog Output Inversion

When ISW = LOW, the analog outputs’ transfer function is

below VRL, while INV is held LOW, and is above VRL, while

INV is held HIGH.

With ISW = HIGH, the analog outputs’ transfer function is

above VRL for VID(0, 2, 4, 6, 8, 10) and is below VRL for

VID(1, 3, 5, 7, 9, 11), while INV is held HIGH. Conversely, the

analog outputs’ transfer function is below VRL for VID(0, 2, 4,

6, 8, 10) and is above VRL for VID(1, 3, 5, 7, 9, 11), while INV is

held LOW.

VRH, VRL Inputs—Full-Scale Video Reference Inputs

Two times the difference between VRH and VRL (analog input

voltages) sets the full-scale output voltage.

VFS = 2 × (VRH − VRL)

Rev. 0 | Page 12 of 16

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