AD73360AR Просмотр технического описания (PDF) - Analog Devices

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AD73360AR

Six-Input Channel Analog Front End

Analog Devices 

t1

t2

t3

Figure 1. MCLK Timing

100␮A IOL

TO OUTPUT

PIN

CL

15pF

100␮A IOH

+2.1V

Figure 2. Load Circuit for Timing Specifications

MCLK

SCLK*

t1

t2

t3

t 13

t5

t6

t4

* SCLK IS INDIVIDUALLY PROGRAMMABLE

IN FREQUENCY (MCLK/4 SHOWN HERE).

Figure 3. SCLK Timing

AD73360

80

70

60

50

40

30

20

10

0

–10

–85 –75 –65 –55 –45 –35 –25 –15

VIN – dBm0

–5

5

3.17

Figure 5a. S/(N+D) vs. VIN (ADC @ 3 V) Over Voiceband

Bandwidth (300 Hz–3.4 kHz)

80

70

60

50

40

30

20

10

0

–10

–85 –75 –65 –55 –45 –35 –25 –15

VIN – dBm0

–5 5

3.17

Figure 5b. S/(N+D) vs. VIN (ADC @ 5 V) Over Voiceband

Bandwidth (300 Hz–3.4 kHz)

SE (I)

THREE-

SCLK (O) STATE

SDIFS (I)

SDI (I)

THREE-

t9

SDOFS (O) STATE

THREE-

STATE

SDO (O)

t7

t8

D15

D14

t 10

t8

t7

D1

D0

t 12

t 11

D15

D2

D1

D0

Figure 4. Serial Port (SPORT)

D15

D15

D14

REV. A

–7–

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