CS5542 Просмотр технического описания (PDF) - Cirrus Logic

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CS5542

22-Bit, Multi-Channel ∆Σ ADC Chip Set

Cirrus Logic 

CS5542 CS5543

Each VREF+ or VREF- input on a CS5542 may re-

quire up to 1 microamp of reference current. The

number of channels which can be supplied from

one voltage reference buffer will depend upon the

buffer’s output impedance and the distance be-

tween the CS5542 and the reference circuitry. A

well-designed voltage reference should be able to

supply 32 channels (16 CS5542s) in a system.

Board Layout

The circuit board containing the CS5542 modulator

should have a ground plane split through middle of

the modulator with pins 2 through 13 over a quiet

analog ground plane. In addition, guarding tech-

niques should be used around the low level inputs

INL, INR, and ICAL. Care must also be exercised

to ensure that the circuit card is manufactured with

good quality to ensure low leakage. After assem-

bly, the card should be cleaned to ensure it is free

from all surface contaminants.

Clock Source

CLKIN must have low jitter; less than 20 psec

RMS. Note that any drift in CLKIN over time or

temperature will show up as a gain error in the

CS5542/CS5543 measurement system; therefore a

stable clock source is highly desirable.

Power Supply

Power supply noise and ripple must be very low

within the passband of the CS5543 digital filter.

This noise and ripple can pass through the ESD

(Electrostatic Discharge) protection diodes at the

INL (INR) pin into the transimpedance stage of the

CS5542 modulator. With the capacitance of this

diode at about 5 pF, and the transimpedance resis-

tor of the first stage at about 2-10 megohm, cou-

pling of supply ripple is going to occur. For this

reason, the noise and ripple on the power supplies

should be low enough that the noise coupled into

the transimpedance stage should remain below the

noise floor of the converter across the bandwidth of

the digital filter. To achieve this, 60 Hz related

noise and ripple should remain below 50 micro-

volts peak-to-peak.

Digital Filter

The digital filter is a linear phase FIR filter. The

filter has a group delay of three conversion words

and an equivalent noise bandwidth of 0.536 of the

output word frequency. Plots for the filter are

shown in the data sheet tables. Coefficients are tab-

ulated in the Appendix of this data sheet.

Joint Test Action Group (JTAG)

Boundary-Scan Interface

The CS5543 is designed for large multi-channel

systems. For this reason the chip is designed to sup-

port the IEEE Standard Access Port and Boundary-

Scan Architecture as defined in IEEE Std. 1149.1-

1990, or P1149.1. This standard defines circuitry

which is built into the an integrated circuit to assist

in the test, maintenance, and support of a system at

the printed circuit board level. The CS5543 in-

cludes circuitry which supports this standard.

It is highly recommended that if this type of test ca-

pability is desired in your system, that you acquire

a copy of the IEEE standard which thoroughly dis-

cusses the IEEE Standard Access Port and Bound-

ary-Scan Architecture as it will only be discussed

briefly here.

The CS5543 includes a TAP (Test Access Port)

made of the following connections: TCK (Test

Clock), TMS (Test Mode Select input), TDI (Test

Data Input), and TDO (Test Data Output). In ad-

dition to the TAP, the test logic includes a TAP

controller, an instruction register, and a set of test

registers. The TAP controller is a synchronous fi-

nite state machine which controls the sequence of

operations necessary to implement the boundary-

scan architecture. Figure 8 illustrates the TAP con-

troller state diagram. The instruction register al-

lows an instruction to be shifted into the design.

20

DS109PP2

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