CS5542 Просмотр технического описания (PDF) - Cirrus Logic

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CS5542

22-Bit, Multi-Channel ∆Σ ADC Chip Set

Cirrus Logic 

CS5542 CS5543

Noise Calibration Register

MSB

2 23 2 22

R0 0

System Offset Registers

Sign Sign Sign

MSW 2 23 2 22 2 21 2 20

Upper 20 Bits

0

LSW 2 23 2 22 2 21 2 20

Lower 22 Bits

LSB

Parity

(Note 1)

21 20

00

LSB

Parity

(Note 1)

21 20

LSB

Parity

(Note 1)

21 20

Gain Registers

Integer

22 21 20

2 0 2 -1 2 -2

Decimal

Reset to Binary 000.11001100110011001000 or 199998(H)

LSB

Parity

(Note 1)

2 -19 LSB

Note 1: All Parity bits are odd.

Table 3. Calibration Registers

should be zeroed before calibrating the Input Offset

Voltage Cal step. The Input Offset Voltage Cal

mode will require 23 filter cycles (a filter cycle is

one output conversion word) to complete. The

CS5543 will not accept new mode commands until

the 23 filter cycles have been completed, even if the

DTEST pins are changed. After the 23 filter cy-

cles, the calibration step is complete. Note that

when the Input Offset Voltage Cal command is ini-

tiated inside the CS5543 decimator, the modulators

of all of the CS5542 chips connected to the CS5543

will execute the calibration step at the same time.

There is no calibration word or register inside the

CS5543 which contains the calibration data for this

calibration step.

The next calibration to be performed is the Noise

Cal. This calibration step is necessary to calibrate

the quantizer threshold of the modulators. This en-

sures linearity in the multi-bit quantizer. The Noise

Cal lasts 409 filter cycles. Upon entering the Noise

Cal mode, the system offset registers are set to 0; all

gain registers are unaffected. The Noise Cal step

can be performed at any time and it can be per-

formed independent of the other calibration steps.

When this step is executed, all eight modulators as-

sociated with a CS5543 calibrate at the same time.

At the end of the Noise Cal step, a 24-bit calibration

word is placed into the Noise Cal register inside the

CS5543.

After the modulators have been calibrated by the

Noise Cal step, the System Offset Cal step is per-

formed. The current present at the INL (INR) input

at the time the System Offset Cal is performed will

treated as the zero point of the converter transfer

function. The System Offset Cal step lasts 1028 fil-

ter cycles. At the end of the System Offset Cal, a

signed 43-bit result is placed into two System Off-

set Cal registers (MSW and LSW; Most Significant

Word and Least Significant Word) inside the

CS5543. After the System Offset Cal is complete,

the next calibration step is a gain calibration. To

perform a gain calibration, an input signal must be

DS109PP2

15

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