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78P2351

Single Channel OC-3/ STM1-E/ E4 LIU

Teridian Semiconductor Corporation 

LOOPBACK MODES

In SW mode, LLBK and RLBK bits in the Signal

Control register are provided to activate the local

and remote analog loopback modes respectively.

In HW mode, the LPBK pin can be used to activate

local and remote analog loopback paths as shown in

the table below.

LPBK pin

Low

Float

High

Loopback Mode

Normal operation

Remote (analog) Loopback:

Recovered receive clock and data

looped back directly to the transmit

driver. The CMI decoder and most of

transmit path is bypassed (including the

redundant Tx monitor output)

Local (analog) Loopback:

Transmit clock and data looped back to

receiver at the analog media interface.

SIDP/N

SICKP/N

PICK

PI[3:0]D

PTOCK

SOCKP/N

SODP/N

PO[3:0]D

POCK

Lock Detect

Tx CDR

FIFO

CMI

Encoder

PMOD, SMOD[1:0], PAR

CMI

Decoder

Rx CDR

Lock Detect

CMI

RLBK,

RDSL

Adaptive

Eq.

LOS Detect

LLBK

Figure 7: Local (Analog) Loopback

ECLP/N

TXCKP/N

CMI2P/N

CMIP/N

RXP/N

SIDP/N

SICKP/N

PICK

PI[3:0]D

PTOCK

SOCKP/N

SODP/N

PO[3:0]D

POCK

Lock Detect

Tx CDR

FIFO

CMI

Encoder

PMOD, SMOD[1:0], PAR

RLBK,

RDSL

ECLP/N

TXCKP/N

CMI2P/N

CMIP/N

CMI

Decoder

Rx CDR

Lock Detect

CMI

Adaptive

Eq.

LOS Detect

LLBK

RXP/N

Figure 8: Remote (Analog) Loopback

78P2351

Single Channel

OC-3/ STM1-E/ E4 LIU

In SW mode only, a Full Remote (digital) Loopback

bit FLBK is also available in the Advanced Tx

Control register. This loopback exercises the entire

Rx and Tx paths of the 78P2351 including the Tx

clock recovery unit. As such, the user must enable

either Serial Plesiochronous or Serial Loop-timing

transmit modes to utilize the Full Remote (digital)

Loopback.

SIxDP/N

SIxCKP/N

PIxCK

PIx[3:0]D

PTOxCK

Lock Detect

Tx CDR

EACH CHANNEL: Tx

FIFO

CMI

Encoder

PMOD, SMOD[1:0], PAR

ECLxP/N

TXxCKP/N

CMIxP/N

RLBK

SOxCKP/N

SOxDP/N

POx[3:0]D

POxCK

CMI

Decoder

Rx CDR

Lock Detect

CMI

EACH CHANNEL: Rx

Adaptive

Eq.

LOS Detect

LLBK

Figure 9: Remote (Digital) Loopback

RXxP/N

INTERNAL POWER-ON RESET

Power-On Reset (POR) function is provided on chip.

Roughly 50 µs after Vcc reaches 2.4V at power up,

a reset pulse is internally generated. This resets all

registers to their default values as well as all state

machines within the transceiver to known initial

values. The reset signal is also brought out to the

PORB pin. The PORB pin is a special function

analog pin that allows for the following:

• Override the internal POR signal by driving in

an external active low reset signal;

• Use the internally generated POR signal to

trigger other resets;

• Add external capacitor to slow down the

release of power-on reset (approximately 8µs

per nF added).

NOTE: Do not pull-up the PORB pin to Vcc or drive

this pin high during power-up. This will prevent the

internal reset generator from resetting the entire chip

and may result in errors.

Page: 8 of 42

2006 Teridian Semiconductor Corporation

Rev. 2.4

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