78P2351 Просмотр технического описания (PDF) - Teridian Semiconductor Corporation

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78P2351

Single Channel OC-3/ STM1-E/ E4 LIU

Teridian Semiconductor Corporation 

REGISTER DESCRIPTION (continued)

LEGEND

TYPE

R/O

R/C

DESCRIPTION

Read only

Read and Clear

TYPE DESCRIPTION

R/W Read or Write

78P2351

Single Channel

OC-3/ STM1-E/ E4 LIU

GLOBAL REGISTERS

ADDRESS 0-0: MASTER CONTROL REGISTER

BIT

NAME

TYPE

DFLT

VALUE

DESCRIPTION

Line Rate Selection:

Selects the line rate as well as the input clock frequency at the

7

E4

R/W

0

CKREFP/N pins.

0: OC-3, STS-3, STM-1 (155.52MHz)

1: E4 (139.264MHz)

6

--

R/W

0

Unused

5

PAR R/W

4:3 CKSL R/W

[1:0]

Serial/Parallel Interface Selection:

Selects the interface to the framer.

0

0: Serial LVPECL

1: 4-bit Parallel CMOS

Reference Clock Frequency Selection:

Selects the reference clock frequency input at CKREFP/N pins.

11: 155.52MHz / 139.264MHz (differential LVPECL)

XX

10: 77.76MHz / NA (single-ended CMOS)

00: 19.44MHz / 17.408MHz (single-ended LVPECL)

Secondary values correspond to E4 frequencies. Default values depend

on the CKSL pin selection upon reset or power up.

2:1

--

R/W

X0 Reserved.

0 SRST R/W

Register Soft-Reset:

0

When this bit is set, all registers are reset to their default values. This

register bit is self-clearing.

Page: 11 of 42

2006 Teridian Semiconductor Corporation

Rev. 2.4

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