78P2351 Просмотр технического описания (PDF) - Teridian Semiconductor Corporation
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78P2351 Datasheet PDF : 42 Pages
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Receive Loss of Signal
The 78P2351 includes a Loss of Signal (LOS)
detector. When the peak value of the received
signal is less than approximately 19dB below
nominal for approximately 110 UI, Receive Loss of
Signal is asserted. The Rx LOS signal is cleared
when the received signal is greater than
approximately 18dB below nominal for 110 UI.
In ECL mode, the LOS signal will be asserted when
there are no transitions for longer than 2.3µs. The
signal is cleared when there are more than 4
transitions in 32 UI. It is generally recommended to
use the LOS status signal from the optical
transceiver module.
During Rx LOS conditions, the receive clock will
remain on the last phase tap of the Rx DLL
outputting a stable clock while the receive data
outputs are squelched and held at logic ‘0’.
Note: Rx Loss of Signal detection is disabled
during Local Loopback and Receive Monitor
Modes.
Receive Loss of Lock
The 78P2351 includes an optional Receiver Loss of
Lock detector that will flag if the recovered Rx clock
frequency differs from the reference clock by more
than ±100ppm in an interval greater than 420µs.
This condition is cleared when the frequencies are
less than ±100ppm off for more than 500µs.
Notes:
1. During Rx Loss of Signal (RLOS), the Rx
Loss of Lock indicator is undefined and may
report either status.
2. For reliable operation, the LOLOR bit in the
Signal Control register should be toggled
upon power-up and configuration.
TRANSMITTER OPERATION
At the media interface, the transmit driver generates
an analog signal for transmission through either a
transformer and 75Ω coaxial cable or directly to a
fiber optics transceiver for electrical to optical
conversion.
At the host interface, the 78P2351 provides a
number interface options for compatibility with most
off-the-shelf framers and custom ASICs. A
selectable 4-bit parallel or nibble interface is
available with both slave or master timing options as
well a serial LVPECL interface with various timing
recovery modes.
78P2351
Single Channel
OC-3/ STM1-E/ E4 LIU
Each of the serial NRZ transmit timing modes can be
configured in HW mode or SW mode as shown in
the table below.
Serial
Mode
HW Control Pins SW Control Bits
SDI_PAR CKMODE PAR SMOD[1:0]
Synchronous
clock + data
Low
Low
0
00
Synchronous
data only
Low
Floating
0
10
Plesiochronous
data only
Low
High
0
01
Loop-timing
n/a
n/a
X
11
Synchronous (Re-timing) Tx Serial Modes
In Figure 1, serial NRZ transmit data is input to the
SIDP/N pins at LVPECL levels. By default, the data
is latched in on the rising edge of SICKP. An
integrated FIFO decouples the on chip and off chip
clocks and re-clocks the data using a clean
synthesized clock generated from the provided
reference clock. As such, the SICKP/N clock
provided by the framer/mapper IC must be source
synchronous with the provided reference clock when
the FIFO is to be used.
System Reference Clock
Framer/
Mapper
NRZ
140 / 155 MHz
SIDP/N
SICKP/N
NRZ
SOCKP/N
140 / 155 MHz
SODP/N
CKREFP/N
TDK
78P2351
CMIP/N
RXP/N
CMI
CMI
XFMR
XFMR
Coax
Coax
Figure 1: Synchronous clock and data available
(Tx CDR bypassed, FIFO enabled)
If an off-chip serial transmit clock is not available, as
in Figure 2, the 78P2351 can recover a Tx clock
from the serial NRZ data input and pass the data
through the clock decoupling FIFO. The data is then
re-clocked or re-timed using a clean synthesized
clock generated from the provided reference clock.
In this mode, the NRZ transmit data must be source
synchronous with the reference clock applied at
CKREFP/N.
System Reference Clock
Framer/
Mapper
NRZ
CKREFP/N
SIDP/N
CMIP/N
NRZ
140 / 155 MHz
SOCKP/N
SODP/N
TDK
78P2351
RXP/N
CMI
CMI
Coax
XFMR
Coax
XFMR
Figure 2: Synchronous data only
(Tx CDR enabled, FIFO enabled)
Page: 5 of 42
2006 Teridian Semiconductor Corporation
Rev. 2.4
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