74HC299(2016) Просмотр технического описания (PDF) - NXP Semiconductors.
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74HC299 Datasheet PDF : 20 Pages
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Nexperia
74HC299
8-bit universal shift register; 3-state
6. Functional description
Table 3. Function table[1]
Input
Response
MR
S1
S0
CP
L
X
X
X
asynchronous reset; Q0 to Q7 = LOW
H
H
H
parallel load; I/On Qn
H
L
H
shift right; DSR Q0, Q0 Q1, etc.
H
H
L
shift left; DSL Q7, Q7 Q6, etc.
H
L
L
X
hold
[1] H = HIGH voltage level;
L = LOW voltage level;
= LOW to HIGH CP transition;
X = don’t care.
7. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min Max Unit
VCC
supply voltage
IIK
input clamping current
IOK
output clamping current
IO
output current
VI < 0.5 V or VI > VCC + 0.5 V
VO < 0.5 V or VO > VCC + 0.5 V
0.5 V < VO < VCC + 0.5 V
standard outputs
0.5
[1]
-
[1]
-
+7 V
20 mA
20 mA
-
25 mA
bus driver outputs
-
35 mA
ICC
supply current
standard outputs
bus driver outputs
-
50 mA
-
70 mA
IGND
ground current
standard outputs
bus driver outputs
50
- mA
70
- mA
Tstg
storage temperature
Ptot
total power dissipation
Tamb = 40 C to +125 C
SO20 package
65 +150 C
[2]
-
500 mW
(T)SSOP20 package
[3]
-
500 mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] Ptot derates linearly at 8 mW/K above 70 C.
[3] Ptot derates linearly at 5.5 mW/K above 60 C.
74HC299
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 26 February 2016
© Nexperia B.V. 2017. All rights reserved
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