21143 Просмотр технического описания (PDF) - Intel
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21143 Datasheet PDF : 52 Pages
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21143
Signal
stop_l
tck
tdi
tdo
tms
tp_rd–
tp_rd+
tp_td–
tp_td– –
tp_td+
tp_td+ +
trdy_l
vcap_h
vdd
vddac
vdd_clamp
vss
xtal1
Table 4. Functional Description of 21143 Signals (Sheet 5 of 6)
Type Pin Number
Description
Stop indicator indicates that the current target is requesting the bus
master to stop the current transaction.
I/O
56
The 21143 responds to the assertion of stop_l when it is the bus
master, either to disconnect, retry, or abort.
JTAG clock shifts state information and test data into and out of the
I
11
21143 during JTAG test operations.
If the JTAG port is unused, this pin should be connected to vss.
I
13
JTAG data in is used to serially shift test data and instructions into the
21143 during JTAG test operations.
O
14
JTAG data out is used to serially shift test data out of the 21143
during JTAG test operations.
I
12
JTAG test mode select controls the state operation of JTAG testing in
the 21143.
I
10
Twisted-pair negative differential receive data from the twisted-pair
lines.
I
9
Twisted-pair positive differential receive data from the twisted-pair
lines.
Twisted-pair negative differential transmit data. The positive and
O
5
negative differential transmit data outputs are combined resistively
O
4
outside the 21143 with equalization to compensate for intersymbol
interference on the twisted-pair medium.
Twisted-pair positive differential transmit data. The positive and
O
6
negative differential transmit data outputs are combined resistively
O
7
outside the 21143 with equalization to compensate for intersymbol
interference on the twisted-pair medium.
Target ready indicates the target agent’s ability to complete the
current data phase of the transaction.
A data phase is completed on any clock when both trdy_l and irdy_l
are asserted. Wait cycles are inserted until both irdy_l and trdy_l are
I/O
52
asserted together.
When the 21143 is the bus master, target ready is asserted by the
bus slave on the read operation, which indicates that valid data is
present on the ad lines. During a write cycle, it indicates that the
target is prepared to accept data.
I
110
Capacitor input for analog phase-locked loop logic.
1, 2, 8, 18, 26,
36, 37, 46, 54, 3.3-V supply input. These pins should be connected to the auxiliary
P 67, 72, 73, 79, power, if such power exists. Otherwise, these pins should be
95, 107, 125, connected to the main power.
136, 141
P
109, 111 Supplies +3.3-V input for analog phase-locked loop logic.
Supplies +5-V or +3.3-V reference for clamp logic.
P
20
This pin is also used to identify the lack of main power when the
auxiliary power is on. This pin should be connected to the main
power.
3, 17, 30, 35,
38, 42, 53, 63,
P 71, 74, 83, 94, Ground pins.
104, 116, 126,
144
I
106
20-MHz crystal input, or crystal oscillator input.This pin should always
be provided with a clock.
14
Preliminary Datasheet
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