21143 Просмотр технического описания (PDF) - Intel

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21143

PCI/CardBus 10/100 Ethernet LAN Controller

Intel 

2.2

21143

Signal

tp_td+ +

xtal1

Table 2. Logic Signals (Sheet 2 of 2)

Pin

Number

Signal

7

trdy_l

106

xtal2

Pin

Number

52

105

Signal

vcap_h

—

Pin

Number

110

—

Signal

vdd (3.3 V)

vddac (3.3 V)

vdd_clamp (5 V or 3.3 V)

Table 3. Power Pins

Pin Number

Signal

1, 2, 8, 18, 26, 36,

37, 46, 54, 67, 72,

73, 79, 95, 107,

125, 136, 141

109, 111

20

vss (GND)

—

—

Pin Number

3, 17, 30, 35, 38,

42, 53, 63, 71, 74,

83, 94, 104, 116,

126, 144

—

—

Signal Reference Tables

The functional grouping of each pin is listed in Section 2.4.

The following terms describe the 21143 pinout:

• Address phase

Address and appropriate bus commands are driven during this cycle.

• Data phase

Data and the appropriate byte enable codes are driven during this cycle.

• _l

All pin names with the _l suffix are asserted low.

The following pins in Table 4 have an internal pull-up:

tms

tdi

br_ce_l

sr_do

mii/sym_tclk

Pin sr_cs has an internal pull-down.

Table 4 uses the following abbreviations:

I = Input

O = Output

I/O = Input/output

O/D = Open drain

P = Power

Preliminary Datasheet

9

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