21143 Просмотр технического описания (PDF) - Intel

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21143

PCI/CardBus 10/100 Ethernet LAN Controller

Intel 

21143

Table 4 provides a functional description of each of the 21143 signals. These signals are listed

alphabetically.

Signal

ad<31:0>

aui_cd–

aui_cd+

aui_rd–

aui_rd+

aui_td–

aui_td+

br_a<0>/

cb_pads_l

br_a<1>

br_ad<7:0>

br_ce_l

c_be_l<3:0>

clkrun_l

Table 4. Functional Description of 21143 Signals (Sheet 1 of 6)

Type Pin Number

Description

23, 24, 25, 27, 32-bit PCI address and data lines. Address and data bits are

28, 29, 31, 32, multiplexed on the same pins. During the first clock cycle of a

39, 40, 41, 43, transaction, the address bits contain a physical address (32 bits).

I/O

44, 45, 47, 48, During subsequent clock cycles, these same lines contain 32 bits of

61, 62, 64, 65, data. A 21143 bus transaction consists of an address phase followed

66, 68, 69, 70, by one or more data phases. The 21143 supports both read and write

76, 77, 78, 80, bursts (in master operation only). Little and big endian byte ordering

81, 82, 84, 85 can be used.

I

138

Attachment unit interface receive collision differential negative data.

I

137

Attachment unit interface receive collision differential positive data.

I

140

Attachment unit interface receive differential negative data.

I

139

Attachment unit interface receive differential positive data.

O

143

Attachment unit interface transmit differential negative data.

O

142

Attachment unit interface transmit differential positive data.

Boot ROM address line bit 0. In a 256KB configuration, this pin also

carries in two consecutive address cycles, boot ROM address bits 16

and 17.

O

88

This pin also determines the type of signals to use for the PCI/

CardBus* output pins, either PCI or CardBus. By default, this pin

selects PCI signaling. To select CardBus signaling, this pin must be

connected to a pull-down resistor.

O

89

Boot ROM address line bit 1. This pin also latches the boot ROM

address and control lines by the two external latches.

Boot ROM address and data multiplexed lines bits 7 through 0. In two

I/O

90, 91, 92, 93,

96, 97, 98, 99

consecutive address cycles, these lines contain the boot ROM

address pins 7 through 2, oe_l and we_l in the first cycle; and these

lines contain boot ROM address pins 15 through 8 in the second

cycle. During the data cycle, bits 7 through 0 contain data.

O

87

Boot ROM or external register chip enable.

Bits 0 through 3 of the bus command and byte enable lines. Bus

command and byte enable are multiplexed on the same PCI pins.

During the address phase of the transaction, these 4 bits provide the

I/O 33, 49, 60, 75 bus command.

During the data phase, these 4 bits provide the byte enable. The byte

enable determines which byte lines carry valid data. For example, bit

0 applies to byte 0, and bit 3 applies to byte 3.

PCI/CardBus clock run indication. The host system asserts this signal

to indicate normal operation of the clock. The host system deasserts

clkrun_l when the clock is going to be stopped or slowed down to a

I/O

nonoperational frequency.

O/D

86

If the clock is needed by the 21143, the 21143 asserts clkrun_l,

requesting normal clock operation to be maintained or restored.

Otherwise, the 21143 allows the system to stop the clock. If this pin is

not connected to the PCI/CardBus bus, it should be connected to a

pull-down resistor.

10

Preliminary Datasheet

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