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ZR36050

JPEG IMAGE COMPRESSION PROCESSOR

Unspecified 

ADVANCE INFORMATION

ZR36050

DATA FLOW CONTROL

Ideally, image data and compressed data flow into or out of the ZR36050 at the maximum possible rate, without breaks. In practice,

however, there are sometimes internal or external conditions that necessitate a break in the data flow.

Encoding

s Missing DSYNC. DSYNC allows the external system, for

example a strip or frame buffer controller, to affect the flow of

image data into the Pixel Interface in encoding.

If DSYNC is not activated together with the last image data

sample of a block, the Pixel Interface stops sampling input

data of the next block, until it samples DSYNC active again.

The ZR36050 completes processing of all data that was input

prior to the missing DSYNC, outputs the DCT coefficients of

the current block, and then enters a Waiting state. The

ZR36050 resumes sampling and processing of image data

upon recieving the next DSYNC activation.

There is no lower or upper limit on the duration of the break

between the missing DSYNC and the next activation of

DSYNC.

s Activation of CBUSY. In Master mode Compressed Data

Transfer, the external compressed data memory control logic

can activate CBUSY at any time, to signal the Compressed

Data Interface that the memory bus is busy.

If the Compressed Data Interface detects CBUSY active, it

completes the current write cycle (if one has started), and

ceases writing compressed data. It resumes writing when

CBUSY becomes inactive.

While CBUSY is active, the Encoding Unit continues to en-

code the coefficients in the Coefficient Buffers until the Code

Buffer is full. The Pixel Interface continues to transfer data

samples to the DCT Unit until three of the four Coefficient

Buffers are full, as described in the next section.

There is no upper limit on the duration of active CBUSY. The

lower limit is one CLK_IN.

s Coefficient Buffers full. If there is a break in the transfer of

compressed data during encoding, because CBUSY was

activated or the Compressed Data Interface bus cycle is long

in Master mode, or because of slow host response in Slave

or DMA modes, the Pixel Interface continues to input image

data until three of the four DCT Coefficient Buffers are full.

When DSYNC of a fourth block arrives, the Pixel Interface

activates STOP, but continues to input the image data of the

fourth block.

If STOP becomes active, the system control logic must halt

the flow of image data to the Pixel Interface at the end of the

current block. If it does not, and STOP is still active, the Co-

efficient Buffers overflow and data is lost, the DATOVF status

bit is set, and the ZR36050 aborts the encoding process and

goes into the Idle state.

Decoding

s Active STOP. In decoding, the system control logic can

break the flow of data samples from the Pixel Interface by

activating STOP. In order to prevent the output of the next

block, STOP has to be activated at least 24 CLK_IN cycles

before the last image sample of the current block that is being

output and must remain active at least until the end of the

current block. While STOP remains active, the ZR36050

continues to decode compressed data, until the Coefficient

Buffers are full.

Upon deactivation of STOP, the ZR36050 outputs the next

DSYNC followed by its corresponding image data block at

least 17 CLK_IN cycles after deactivation of STOP.

s Activation of CBUSY. In Master mode Compressed Data

Transfer, the external compressed data memory control logic

can activate CBUSY at any time, to signal the Compressed

Data Interface that the memory bus is busy.The Compressed

Data Interface strobes CBUSY on the rising edge of CLK_IN.

If CBUSY is activated at least one CLK_IN prior to the begin-

ning of a read or write cycle, then the next read or write cycle

will not be performed. It resumes reading when CBUSY be-

comes inactive.

There is no upper limit on the duration of active CBUSY. The

lower limit is one CLK_IN.

s Slow compressed data transfer. If Compressed Data

Transfer is slowed, because CBUSY was activated or the

Compressed Data Interface bus cycle is long in Master

mode, or because of slow host response in Slave or DMA

modes, the next Coefficient Buffer may not be fully

assembled by the time it is needed for continuous image data

flow.

In this case, the Pixel Interface does not activate DSYNC to-

gether with the last output sample of the current block, and

therefore does not immediately start to output the data sam-

ples of the next block. As soon as the next complete block

has been decoded and is ready for output, the Pixel Interface

activates DSYNC followed by the image data.

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