UPD72850A Просмотр технического описания (PDF) - NEC => Renesas Technology

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UPD72850A

IEEE1394 400Mbps PHY

NEC => Renesas Technology 

µPD72850A

3.4 PLL and Crystal Oscillation Circuit

3.4.1 Crystal Oscillation Circuit

To supply the clock of 24.576 MHz ± 100 ppm, use an external capacitor of 10 pF and a crystal of 50 ppm.

3.4.2 PLL

The crystal oscillator multiplies the 24.576 MHz frequency by 16 (393.216 MHz).

3.5 PC0-PC2, CMC

CMC shows the bus manager function which corresponds to the c bit of the Self_ID packet and the Contender bit

in the PHY register when the input is High.

The value of CMC can be changed with software through the Link layer; this pin sets the initial value during Power-

on Reset. Use a pull-up or pull-down resistor of 10 kΩ, based on the device’s specification.

The PC0-PC2 pin corresponds to the power field of the Self_ID packet and Pwr_class in the PHY register. Refer to

Section 4.3.4.1 of the IEEE1394-1995 specification for information regarding the Pwr_class. The value of Pwr can be

changed with software through the Link layer controller; this pin sets the initial value during Power-on Reset. Use a

pull-up or pull-down resistor of 10 kΩ based on the application.

3.6 RESETB

Connect an external capacitor of 0.1 µF between the pins RESETB and GND. If the voltage drops below 0 V, a

reset pulse is generated. All of the circuits are initialized, including the contents of the PHY register.

3.7 RI1, RI0

Connect an external resistor of 9.1 kΩ to limit the LSI’s current.

20

Data Sheet S14452EJ1V0DS00

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