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V54C316162V

200/183/166/143 MHz 3.3 VOLT/ 4K REFRESH ULTRA HIGH PERFORMANCE 1M X 16 SDRAM 2 BANKS X 512Kbit X 16

Mosel Vitelic, Corp 

MOSEL VITELIC

V54C316162V

Address Input for Mode Set (Mode Register Operation)

A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus (Ax)

Write Burst Length

Test

Mode

CAS Latency BT Burst Length Mode Register

Write Burst Length Test Mode

A9

Length

0

Burst

1

Single Bit

A8 A7 Mode

0

0

Mode Reg

Set

CAS Latency

A6 A5 A4

0

0

0

0

0

1

0

1

0

0

1

1

1

0

1

1

1

0

1

1

1

Latency

Reserve

Reserve

2

3

Reserve

Reserve

Reserve

Power On and Initialization

The default power on state of the mode register is

supplier specific and may be undefined. The

following power on and initialization sequence

guarantees the device is preconditioned to each

users specific needs. Like a conventional DRAM,

the Synchronous DRAM must be powered up and

initialized in a predefined manner. During power on,

all VCC and VCCQ pins must be built up

simultaneously to the specified voltage when the

input signals are held in the “NOP” state. The power

on voltage must not exceed VCC+0.3V on any of

the input pins or VCC supplies. The CLK signal

must be started at the same time. After power on,

an initial pause of 200 µs is required followed by a

precharge of both banks using the precharge

command. To prevent data contention on the DQ

bus during power on, it is required that the DQM and

CKE pins be held high during the initial pause

period. Once all banks have been precharged, the

Mode Register Set Command must be issued to

initialize the Mode Register. A minimum of eight

Auto Refresh cycles (CBR) are also required.These

may be done before or after programming the Mode

Register. Failure to follow these steps may lead to

unpredictable start-up modes.

Burst Type

A3

Type

0

Sequential

1

Interleave

Burst Length

Length

A2 A1 A0

Sequential Interleave

000

1

1

001

2

2

010

4

4

011

8

8

1 0 0 Reserve Reserve

1 0 1 Reserve Reserve

1 1 0 Reserve Reserve

1 1 1 Full Page Reserve

Programming the Mode Register

The Mode register designates the operation

mode at the read or write cycle. This register is di-

vided into 4 fields. A Burst Length Field to set the

length of the burst, an Addressing Selection bit to

program the column access sequence in a burst

cycle (interleaved or sequential), a CAS Latency

Field to set the access time at clock cycle and a Op-

eration mode field to differentiate between normal

operation (Burst read and burst Write) and a special

Burst Read and Single Write mode. The mode set

operation must be done before any activate com-

mand after the initial power up. Any content of the

mode register can be altered by re-executing the

mode set command. All banks must be in pre-

charged state and CKE must be high at least one

clock before the mode set operation. After the mode

register is set, a Standby or NOP command is

required. Low signals of RAS, CAS, and WE at the

positive edge of the clock activate the mode set

operation. Address input data at this timing defines

parameters to be set as shown in the previous table.

V54C316162V Rev. 2.9 September 2001

5

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