PCD5002 Просмотр технического описания (PDF) - Philips Electronics
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PCD5002 Datasheet PDF : 48 Pages
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Philips Semiconductors
Advanced POCSAG and APOC-1 Paging
Decoder
Product specification
PCD5002
This can be applied by the microcontroller, or via a suitable
RC power-on reset circuit connected to the RST input.
Reset circuit details and conditions during and after a reset
are described in Chapter 9.
8.9 Bit rates
The PCD5002 can be configured for data rates of 512,
1200 or 2400 bits/s by SPF programming. These data
rates are derived from a single 76.8 kHz oscillator
frequency.
8.10 Oscillator
The oscillator circuit is designed to operate at 76.8 kHz.
Typically, a tuning fork crystal will be used as a frequency
source. Alternatively, an external clock signal can be
applied to pin XTAL1 (amplitude = VDD to VSS), but a
slightly higher oscillator current is consumed. A 2.2 MΩ
feedback resistor connected between XTAL1 and XTAL2
is required for proper operation.
To allow easy oscillator adjustment (e.g. by a variable
capacitor) a 32.768 kHz reference frequency can be
selected at output REF by SPF programming.
8.11 Input data processing
Data input is binary and fully asynchronous. Input bit rates
of 512, 1200 and 2400 bits/s are supported. As a
programmable option, the polarity of the received data can
be inverted before further processing.
The input data is noise filtered by a digital filter. Data is
sampled at 16 times the data rate and averaged by
majority decision.
The filtered data is used to synchronize an internal clock
generator by monitoring transitions. The recovered clock
phase can be adjusted in steps of 1⁄8 or 1⁄32 bit period per
received bit.
The larger step size is used when bit synchronization has
not been achieved, the smaller when a valid data
sequence has been detected (e.g. preamble or sync
word).
8.12 Battery saving
Current consumption is reduced by switching off internal
decoder sections whenever the receiver is not enabled.
To further increase battery efficiency, reception and
decoding of an address codeword is stopped as soon as
the uncorrected address field differs by more than 3 bits
from the enabled RICs. If the next codeword must be
received again, the receiver is re-enabled thus observing
the programmed establishment times tRXE and tROE.
The current consumption of the complete pager can be
minimized by separately activating the RF oscillator circuit
(using output ROE) before activating the rest of the
receiver. This is possible using the UAA2082 receiver
which has external biasing for the oscillator circuit.
8.13 POCSAG Synchronization strategy
In the ON status the PCD5002 synchronizes to the
POCSAG data stream by the Philips ACCESS® algorithm.
A flow diagram is shown in Fig.4. Where ‘sync word’ is
used, this implies both the standard POCSAG sync word
and any enabled User Programmable Sync Word
(UPSW).
Several modes of operation can be distinguished
depending on the synchronization state. Each mode uses
a different method to obtain or retain data synchronization.
The receiver and oscillator enable outputs (RXE and ROE
respectively) are switched accordingly, with the
appropriate establishment times (tRXON and tROON
respectively).
Before comparing received data with preamble, an
enabled sync word or programmed user addresses, the
appropriate error correction is applied.
Initially, after switching to the ON status, the decoder is in
switch-on mode. Here the receiver will be enabled for a
period up to 3 batches, testing for preamble and the sync
word. Failure to detect preamble or the sync word will
cause the device to switch to the ‘carrier off’ mode.
When preamble is detected it will cause the device to
switch to the preamble receive mode, in which a sync
word is searched for. The receiver will remain enabled
while preamble is detected. When neither sync word nor
preamble is found within a 1 batch duration the ‘carrier off’
mode is entered.
Upon detection of a sync word the data receive mode is
entered. The receiver is activated only during enabled user
address frames and sync word periods. When an enabled
user address has been detected, the receiver will be kept
enabled for message codeword reception until the call
termination criteria are met.
During call reception data bytes are stored in an internal
SRAM buffer, capable of storing 2 batches of message
data.
Messages are transmitted contiguously, only interrupted
by sync words at the beginning of each batch.
1997 Jun 24
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