ISP1161 Просмотр технического описания (PDF) - Philips Electronics

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ISP1161

Full-speed Universal Serial Bus single-chip host and device controller

Philips Electronics 

Philips Semiconductors

ISP1161

Full-speed USB single-chip host and device controller

Table 2: Pin description for LQFP64 …continued

Symbol [1]

Pin Type Description

DREQ2

26 O

DC’s DMA request output (programmable polarity); signals

to the DMA controller that the ISP1161 wants to start a

DMA transfer; see DC’s hardware configuration register

(BAH/BBH)

DACK1

27 I

HC’s DMA acknowledge input. Active level programmable.

See the HcHardwareConfiguration register (20H/A0H)

DACK2

28 I

DC’s DMA acknowledge input. Active level programmable.

See DC’s hardware configuration register (BAH/BBH)

INT1

29 O

HC’s interrupt output; programmable level, edge triggered

and polarity; see HcHardwareConfiguration register (20H,

A0H)

INT2

30 O

DC’s interrupt output; programmable level, edge triggered

and polarity; see DC’s hardware configuration register

(BAH, BBH)

TEST

31 O

Test output; this pin is used for test purposes only.

RESET

32 I

reset input (Schmitt trigger); a LOW level produces an

asynchronous reset

NDP_SEL

33 I

number of downstream ports:

0 — select 1 downstream port

1 — select 2 downstream ports

only changes the value of the NDP field in the

HcRhDescriptorA register; there will always be two ports

present in the UsbSlaveHost

EOT

34 I

DMA master device to inform ISP1161 of end of DMA

transfer (Active level is programmable), see

HcHardwareConfiguration register (20H/A0H)

DGND

35 -

digital ground

D_SUSPEND 36 O

DC’s suspend’ state indicator output; active level

programmable

D_WAKEUP 37 I

DC’s wake-up input (edge triggered); a LOW-to-HIGH

transition generates a remote wake-up from ‘suspend’

state

GL

38 O

GoodLink LED indicator output (open-drain); the LED is

default ON, blinks OFF upon USB traffic; blinking can be

disabled by setting bit 1 of MODE register to a 1

D_VBUS

39 I

H_WAKEUP 40 I

DC’s USB upstream port VBUS sensing input

HC’s wake-up input (edge triggered); a LOW-to-HIGH

transition generates a remote wake-up from ‘suspend’

state

CLKOUT

41 O

programmable clock output (3 to 48 MHz); default 12 MHz

H_SUSPEND 42 O

HC’s suspend’ state indicator output; active level

programmable

XTAL1

43 I

crystal oscillator input (6 MHz); connect a fundamental

mode or third-overtone, parallel-resonant crystal or an

external clock source (leaving pin XTAL2 unconnected)

9397 750 08313

Product data

Rev. 01 — 3 July 2001

© Philips Electronics N.V. 2001. All rights reserved.

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