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ISP1161 Просмотр технического описания (PDF) - Philips Electronics

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ISP1161 Datasheet PDF : 127 Pages
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Philips Semiconductors
ISP1161
Full-speed USB single-chip host and device controller
Table 2: Pin description for LQFP64 …continued
Symbol [1]
Pin Type Description
D6
6
I/O
bit 6 of bidirectional data; slew-rate controlled; TTL input;
three-state output
D7
7
I/O
bit 7 of bidirectional data; slew-rate controlled; TTL input;
three-state output
DGND
8
-
digital ground
D8
9
I/O
bit 8 of bidirectional data; slew-rate controlled; TTL input;
three-state output
D9
10 I/O
bit 9 of bidirectional data; slew-rate controlled; TTL input;
three-state output
D10
11 I/O
bit 10 of bidirectional data; slew-rate controlled; TTL input;
three-state output
D11
12 I/O
bit 11 of bidirectional data; slew-rate controlled; TTL input;
three-state output
D12
13 I/O
bit 12 of bidirectional data; slew-rate controlled; TTL input;
three-state output
D13
14 I/O
bit 13 of bidirectional data; slew-rate controlled; TTL input;
three-state output
DGND
15 -
digital ground
D14
16 I/O
bit 14 of bidirectional data; slew-rate controlled; TTL input;
three-state output
D15
17 I/O
bit 15 of bidirectional data; slew-rate controlled; TTL input;
three-state output
DGND
18 -
digital ground
Vhold1
19 -
voltage holding pin; this pin is internally connected to the
Vreg(3.3) and Vhold2 pins. When the VCC pin is connected to
+5 V, this pin will output 3.3 V, hence it should not be
connected to +5 V. When the VCC pin is connected to
+3.3 V, this pin can either be connected to +3.3 V or left
unconnected. In all cases this pin should be decoupled to
DGND.
n.c.
20 -
no connection
CS
21 I
chip select input
RD
22 I
read strobe input
WR
23 I
write strobe input
Vhold2
24 -
voltage holding pin; this pin is internally connected to the
Vreg(3.3) and Vhold1 pins. When the VCC pin is connected to
+5 V, this pin will output 3.3 V, hence it should not be
connected to +5 V. When the VCC pin is connected to
+3.3 V, this pin can either be connected to +3.3 V or left
unconnected. In all cases this pin should be decoupled to
DGND.
DREQ1
25 O
HC’s DMA request output (programmable polarity); signals
to the DMA controller that the ISP1161 wants to start a
DMA transfer; see HcHardwareConfiguration register
(20H/A0H)
9397 750 08313
Product data
Rev. 01 — 3 July 2001
© Philips Electronics N.V. 2001. All rights reserved.
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