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IDT72103

CMOS PARALLEL-SERIAL FIFO 2,048 x 9 and 4,096 x 9

Integrated Device Technology 

IDT72103, IDT72104

CMOS PARALLEL-SERIAL FIFO 2,048 x 9 AND 4,096 x 9

INDUSTRIAL TEMPERATURE RANGE

PIN DESCRIPTION

Symbol

Name

I/O

Description

D0-D8 Data Inputs

I/O In a parallel input configuration – data inputs for 9-bit wide data.

Serial Input Word

In a serial input configuration – one of the nine output pins is used to select the serial input

Width Select

RS Reset

W

Write

word width.

I When RS is set low, internal READ and WRITE pointers are set to the first location of the RAM

array. EF, EF+1, AEF are all LOW after a reset, while FF, FF-1, HF are HIGH after a reset.

I A parallel word write cycle is initiated on the falling edge of W if the FF is high. When the FIFO

is full, FF will go low inhibiting further write operations to prevent data overflow. In a serial

input configuration, data bits are clocked into the input shift register and the write pointer does

not advance until a full parallel word is assembled. One of the pins, Di, is connected to W and

R

Read

advances the write pointer every i-th serial input clock.

I A read cycle is initiated on the falling edge of R if the EF is HIGH. After all the data from the

FIFO has been read EF will go LOW inhibiting further read operations. In a serial output

FL/RT First Load/

Retransmit

Xl

Expansion In

OE Output Enable

configuration, a data word is read from memory into the output shift register. One of the pins,

Qj, is connected to R and advances the read pointer every j-th serial output clock.

I This is a dual-purpose pin. In multiple-device mode, FL/RT is grounded to indicate the first

device loaded. In single-device mode, FL/RT acts as the retransmit input. Single-device mode

is initiated by grounding the XI pin.

I In single-device mode, XI is grounded. In depth expansion or daisy chain mode, XI is con-

nected to the XO pin of the previous device.

I When OE is LOW, both parallel and serial outputs are enabled. When OE is HIGH, the parallel

output buffers are placed in a high-impedance state.

Q0-Q8 Data Outputs/Serial

O In a parallel output configuration - data outputs for 9-bit wide data. In a serial output

Output Word Width Select

configuration - one of nine output pins used to select the serial output word width.

FF Full Flag

O FF is asserted LOW when the FIFO is full and further write operations are inhibited. When

the FF is HIGH, the FIFO is not full and data can be written into the FIFO.

FF-1 Full-1 Flag

O FF-1 goes LOW when the FIFO memory array is one word away from being full. It will remain

XO/HF Expansion Out/

Half-Full Flag

LOW when every memory location is filled.

O HF is LOW when the FIFO is more than half-full in the single device or width expansion modes.

The HF will remain LOW until the difference between the write and read pointers is less than

or equal to one-half of the FIFO memory.

In depth expansion mode, a pulse is written from XO to XI of the next device when the last

location in the FIFO is filled. Another pulse is sent from XO to Xl of the next device when the

AEF Almost-Empty/

last FIFO location is read.

O When AEF is LOW, the FIFO is empty to 1/8 full or 7/8 full to completely full. If AEF is HIGH,

Almost-Full Flag

EF+1 Empty+1 Flag

EF Empty Flag

then the FIFO is greater than 1/8 full, but less than 7/8 full.

O EF+ 1 is LOW when there is zero or one word in the FIFO memory array.

O EF goes LOW when the FIFO is empty and further read operations are inhibited. FF is HIGH

when the FIFO is not empty and data reads are permitted.

Sl

Serial Input Expansion

I Data input for serial data.

SO Serial Output Expansion O Data output for serial data.

SICP Serial Input Clock

I This pin is the serial input clock. On the rising edge of the SICP signal, new serial data bits

are read into the serial input shift register.

SOCP Serial Output

I This pin is the serial output clock. On the rising edge of the SOCP signal, new serial data bits

Clock

are read from the serial output shift register.

SIX Serial Input

I SIX controls the serial input expansion for word widths greater than 9 bits. In a serial input

Expansion

configuration, the SIX pin of the least significant device is tied HIGH. The SIX pin of all other

devices is connected to the D8 pin of the previous device. In parallel input configurations or

serial input configurations of 9 bits or less, SIX is tied HIGH.

SOX Serial Output

I SOX controls the serial output expansion for word widths greater than 9 bits. In a serial output

Expansion

configuration, the SOX pin of the least significant device is tied HIGH. The SOX pin of all other

devices is connected to the Q8 pin of the previous device. In parallel output configurations or

SI/PI Serial/Parallel Input

SO/PO Serial/Parallel Output

serial output configurations of 9 bits or less, SOX is tied HIGH.

I When this pin is HIGH, the FIFO is in a parallel input configuration and accepts input data through

D0-D8. When SI/PI is LOW, the FIFO is in a serial input configuration and data is input through Sl.

I When this pin is HIGH, the FIFO is in a parallel output configuration and sends output data through

Q0-Q8. When SO/PO is LOW the FIFO is in a serial output configuration and data is input through SO.

GND Ground

Five ground pins for the PLCC.

VCC Power

One + 5V power pin.

2753 tbl 04

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