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FCT162511AT
(Rev.:2001)

FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY

Integrated Device Technology 

IDT54/74FCT162511AT/CT

FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER

MILITARY AND INDUSTRIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS

V CC

7.0V

V IN

Pulse

Generator

D.U.T.

RT

V OUT

50pF

CL

500Ω

500Ω

SWITCH POSITION

Test

Open Drain

Disable Low

Enable Low

All Other Tests

Switch

Closed

Open

DEFINITIONS:

CL = Load capacitance: includes jig and probe capacitance.

RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.

Test Circuits for All Outputs

DATA

INPUT

TIMING

INPUT

tSU

tH

ASYNCHRONOUS CONTROL

PRESET

tREM

CLEAR

ETC.

SYNCHRONOUS CONTROL

PRESET

CLEAR

CLOCK ENABLE

tSU

tH

ETC.

Set-up, Hold, and Release Times

SAME PHASE

INPUT TRANSITION

OUTPUT

OPPOSITE PHASE

INPUT TRANSITION

tPLH

tPLH

tPHL

tPHL

Propagation Delay

3V

1.5V

0V

3V

1.5V

0V

3V

1.5V

0V

3V

1.5V

0V

LOW -HIGH-LOW

PULSE

H IG H -L O W -H IG H

PULSE

tW

Pulse Width

1.5V

1.5V

3V

1.5V

0V

VOH

1.5V

VOL

3V

1.5V

0V

ENABLE

CONTROL

INPUT

OUTPUT

NORMALLY

LOW

tPZL

SW ITC H

CLOSED

tPZH

OUTPUT

NORMALLY

HIGH

SWITCH

OPEN

DISABLE

3.5V

1.5V

tPHZ

tPLZ

0.3V

1.5V

0V

0.3V

3V

1.5V

0V

3.5V

VOL

VOH

0V

Enable and Disable Times

NOTES:

1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.

2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.

9

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