FCT162511AT(2001) Просмотр технического описания (PDF) - Integrated Device Technology
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FCT162511AT
(Rev.:2001)
(Rev.:2001)
Integrated Device Technology
FCT162511AT Datasheet PDF : 10 Pages
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IDT54/74FCT162511AT/CT
FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER
PIN CONFIGURATION
OEAB
1
LEAB
2
PA1
3
GND
4
A0
5
A1
6
VCC
7
A2
8
A3
9
A4
10
A5
11
A6
12
A7
13
GND
14
PERA
15
A8
16
A9
17
A10
18
A11
19
A12
20
A13
21
VCC
22
A14
23
A15
24
GND
25
PA2
26
OEBA
27
LEBA
28
56
GEN/CHK
55
CLKAB
54
PB1
53
GND
52
B0
51
B1
50
VCC
49
B2
48
B3
47
B4
46
B5
45
B6
44
B7
43
PERB
42
GND
41
B8
40
B9
39
B10
38
B11
37
B12
36
B13
35
VCC
34
B14
33
B15
32
GND
31
PB2
30
CLKBA
29
ODD/EVEN
SSOP/ TSSOP/ CERPACK
TOP VIEW
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Description
Max
Unit
VTERM(2) Terminal Voltage with Respect to GND
–0.5 to 7
V
VTERM(3) Terminal Voltage with Respect to GND –0.5 to VCC+0.5 V
TSTG Storage Temperature
–65 to +150
°C
IOUT
DC Output Current
–60 to +120
mA
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. All device terminals except FCT162XXX Output and I/O terminals.
3. Output and I/O terminals for FCT162XXX.
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Symbol
Parameter(1)
Conditions Typ. Max. Unit
CIN
Input Capacitance
VIN = 0V
3.5
6
pF
CI/O
I/O Capacitance
VOUT = 0V
3.5
8
pF
CO
Open Drain
Capacitance
VOUT = 0V
3.5
6
pF
PIN DESCRIPTION
Pin Names
OEAB
OEBA
LEAB
Description
A-to-B Output Enable Input (Active LOW)
B-to-A Output Enable Input (Active LOW)
A-to-B Latch Enable Input
LEBA
B-to-A Latch Enable Input
CLKAB
A-to-B Clock Input
CLKBA
B-to-A Clock Input
Ax
Bx
PERA
PERB
PAx(1)
PBx
ODD/EVEN
GEN/CHK
A-to-B Data Inputs or B-to-A 3-State Outputs
B-to-A Data Inputs or A-to-B 3-State Outputs
Parity Error (Open Drain) on A Outputs
Parity Error (Open Drain) on B Outputs
A-to-B Parity Input, B-to-A Parity Output
B-to-A Parity Input, A-to-B Parity Output
Parity Mode Selection Input
A to B Port Generate or Check Mode Input
NOTE:
1. The PAx pin input is internally disabled during parity generation. This means that when
generating parity in the A to B direction there is no need to add a pull up resistor to
guarantee state. The pin will still function properly as the parity output for the B to A
direction.
3
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