CY7C008(2004) Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C008 Datasheet PDF : 19 Pages
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Switching Waveforms (continued)
Write Cycle No. 1: R/W Controlled Timing[27, 28, 29, 30]
tWC
ADDRESS
OE
[31]
CE
R/W
DATA OUT
DATA IN
tAW
tSA
tPWE[30]
NOTE 33
tHZWE[32]
tSD
Write Cycle No. 2: CE Controlled Timing[27, 28, 29, 34]
tWC
ADDRESS
[28]
CE
tSA
R/W
tAW
tSCE
tSD
DATA IN
CY7C008/009
CY7C018/019
tHZOE[32]
tHA
tLZWE
tHD
NOTE 33
tHA
tHD
Notes:
27. R/W must be HIGH during all address transitions.
28. A write occurs during the overlap (tSCE or tPWE) of a LOW CE or SEM.
29. tHA is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
30. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data to be placed on
the bus for the required tSD. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tPWE.
31. To access RAM, CE = VIL, SEM = VIH.
32. Transition is measured ±500 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested.
33. During this period, the I/O pins are in the output state, and input signals must not be applied.
34. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
Document #: 38-06041 Rev. *C
Page 10 of 19
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