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FS61850-01

1:10 HSTL SMBus Zero-Delay Clock Buffer IC

AMI Semiconductor 

FS61850-01

1:10 HSTL SMBus Zero-Delay Clock Buffer IC

Advance Information

AMERICAN MICROSYSTEMS, INC.

November 2000

Table 10: Serial Interface Timing Specifications

Unless otherwise stated, all power supplies = 2.5V, no load on any output, and ambient temperature TA = 25°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and

are not currently production tested to any specific limits. MIN and MAX characterization data are ± 3σ f rom typical.

PARAMETER

Clock frequency

Bus free time between STOP and START

Set up time, START (repeated)

Hold time, START

Set up time, data input

Hold time, data input

Output data valid from clock

Rise time, data and clock

Fall time, data and clock

High time, clock

Low time, clock

Set up time, STOP

SYMBOL

CONDITIONS/DESCRIPTION

fSCL

tBUF

tsu:STA

thd:STA

tsu:DAT

thd:DAT

tAA

tr

tf

tHI

tLO

tsu:STO

SCL

SDA

SDA

Minimum delay to bridge undefined

region of the fall-ing edge of SCL to

avoid unintended START or STOP

SDA, SCL

SDA, SCL

SCL

SCL

STANDARD MODE

MIN.

MAX.

0

100

4.7

4.7

4.0

250

0

3.5

1000

300

4.0

4.7

4.0

UNITS

kHz

µs

µs

µs

ns

µs

µs

ns

ns

µs

µs

µs

Figure 5: Bus Timing Data

SCL

SDA

tsu:STA

thd:STA

START

ADDRESS OR

DATA VALID

DATA CAN

CHANGE

Figure 6: Data Transfer Sequence

SCL

tF

tLO

tsu:STA

thd:STA

SDA

IN

tAA

SDA

OUT

tHI

thd:DAT

tAA

tsu:DAT

tsu:STO

STOP

tR

tsu:STO

tBUF

ISO9001

QS9000

8

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