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CMX624

V.23 / Bell 202 Modem

CML Microsystems Plc 

V23 / Bell 202 Modem

CMX624

1.5.10 Tx/Rx UART

This block connects the µC, via the ‘C-BUS’ interface, to the received data from the FSK Demodulator and

to the transmit data input to the FSK Modulator.

As part of this function, the block can be programmed to convert data to be transmitted from 7 or 8-bit

bytes to asynchronous data characters, adding Start and Stop bits and - optionally - a parity bit to the data

before passing it to the FSK Modulator. Similarly, in the receive direction it can extract data bits from

asynchronous characters coming from the FSK Demodulator, stripping off the Start and Stop bits and

performing an optional Parity check on the received data before passing the result over the ‘C-BUS’ to the

µC. Bits 0-3 of the SETUP Register control the number of Stop and Data bits and the Parity options for

both receive and transmit directions.

Data to be transmitted should be loaded by the µC into the TX DATA Register when the Tx Data Ready bit

(bit 0) of the FLAGS Register goes high. It will then be treated by the Tx UART block in one of two ways,

depending on the setting of bit 3 of the FSK MODE Register:

If the bit is ‘0’ (‘Tx Sync’ mode) then the 8 bits from the TX DATA Register will be transmitted

sequentially at 75, 150 or 1200bps, LSB (D0) first.

If bit 3 of the FSK MODE Register is ‘1’ (‘Tx Async’) then bits will be transmitted as asynchronous

data characters at 75, 150 or 1200 bps according to the following format:

One Start bit (Space).

7 or 8 Data bits from the TX DATA Register (D0-D6 or D0-D7) as determined by bit 0 of

the SETUP Register. LSB (D0) transmitted first.

Optional Parity bit (even or odd parity) as determined by bits 1 and 2 of the SETUP

Register.

One or Two Stop bits (Mark) as determined by bit 3 of the SETUP Register.

In both cases data will only be transmitted if bit 1 of the FSK MODE Register is set to ‘1’.

Failure to load the TX DATA Register with a new value when required will result in bit 1 (Tx Data

Underflow) of the FLAGS Register being set to ‘1’ and if the ‘Tx Async’ mode of operation had been

selected then a continuous Mark (‘1’) signal will then be transmitted until a new value is loaded into TX

DATA, whereas in ‘Tx Sync’ mode the byte already in the TX DATA Register will be re-transmitted.

Figure 6a Transmit UART Function (Async)

 2003 CML Microsystems Plc

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