MSM6782-01 Просмотр технического описания (PDF) - Oki Electric Industry

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MSM6782-01

Real time clock

Oki Electric Industry 

MSM6782-01

¡ Semiconductor

• fr Flag

The fr flag bit indicates a carry when the CE input is at “H” level.

This bit is checked when the clock/calendar registers are read out. If this bit is set to “1”, it

is possible to read out these registers without using the HOLD bit.

This bit is cleared by setting the CE input to “L” level.

CD REGISTER (Control D Register)

• 30-sec ADJ (30-second adjustment bit)

When writing to this bit, if the second digits are smaller than 30, the second digits are reset

to 00, and if it is larger than 30, the second digits are reset to 00 and a carry into the minute

digit is executed. Data can not be written into the S1 ~ W registers and a “1” can not be written

into the REST bit of the CF register 125ms after writing into this bit because internal processing

is being executed. This bit holds “1” 125ms after writing, and returns to “0” automatically.

Therefore, data should be written into the S1 ~ W registers after checking that this bit has

returned to “0”.

• IRQ - F

This bit is set to “1” and the STD.P output goes low in the cycle period specified by the

combination of bit t1 and bit t0 of the CE register. If INT/STND = “1”, the bit status “1” and

output level “L” are kept until reading of the CD register is complete.

After the CD register is read out, the IRQ - F bit returns to “0” and the STD.P output goes into

high impedance automatically.

If INT/STD = “0”, the IRQ -F bit returns to “0” about 7.8 ms later or immediately after the CD

register is read out, and the STD.P returns to “high impedance” about 7.8 ms later.

• CAL/HW (Clock range switching bit)

CAL/HW = “1” : Seconds, minutes, hours, days, month, year, day of week

CAL/HW = “0” : Seconds, minutes, hours, day of week

If this bit is “0”, the D1, D10, MO1, MO10, Y1, Y10 registers can be used as 4-bit data RAM and

the * bits and fr bits of the D10 and MO10 registers also can be used as independent RAM,

because these registers stop clock operation.

• HOLD

“1” of this bit inhibits a carry into 1-second digit.

Clock operation continues before reaching a second.

During Hold = “1”, if a carry occurs, the S1 counter is incremented by 1 second after Hold =

“0”.

This bit is cleared to zero by writing “0”.

128

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