MSM6782-01 Просмотр технического описания (PDF) - Oki Electric Industry

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MSM6782-01

Real time clock

Oki Electric Industry 

¡ Semiconductor

MSM6782-01

CE REGISTER (Control E Register)

• t1, t0

INT/STND bit = “1” : Setting of interrupt period

INT/STND bit = “0” : Setting of periodic waveform

t1 t0

Period

0 0 1/64 second

0 1 1 second

1 0 1 minute

1 1 1 hour

The duration that the periodic waveform output is at “L” level is about 7.8ms.

t1 and t0 determine the output timing of the STD.P output.

e.g.) When t1=“1”, t0=“1”, MASK=“0”

12:00PM

1:00PM

STD.P output

when INT/STND="1"

High impedance

"L" level

STD.P output

when INT/STND="0"

High impedance

"L" level

When writing into the 30-sec ADJ bit, a carry can occur.

Therfore, if (t1, t0) = (1, 0), (1, 1), the STD.P output may sometime be at “L” level. When INT/

STND=”0", this “L” level is kept for a maximum of 9.8ms after under-second digits in 30-sec

ADJ is cleared (the 30-sec ADJ flag returns to “0”).

If the selected interrupt period is 1 second, 1 minute, or 1 hour, and if a carry occurs during the

time the S1, S10, MI1, MI10 registers are overwritten using the HOLD bit, and if data written

in these registers determines the interrupt timing set by the carry, the STD.P output will go to “L”

level after HOLD=”0". (IRQ-F will is set to “1”)

In other cases, writing to the S1, S10, MI1, MI10, H1 registers do not change the STD.P output.

• INT/STND (interrupt-to-Standard waveform switching bit)

INT/STND = “1” : “1” of the IRQ-F bit and “L” level on the STD.P output are kept until IRQ-

F (CD register) is read out.

INT/STND = “0” : “1” of the IRQ-F bit returns to “0” after a certain time elapses (after about

7.8ms) or when IRQ-F is read out.

“L” level on the STD.P output returns to high impedance after a certain

time elapses.

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