MSM6782-01 Просмотр технического описания (PDF) - Oki Electric Industry
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MSM6782-01 Datasheet PDF : 17 Pages
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MSM6782-01
¡ Semiconductor
PIN DESCRIPTION
• STD.P (Pin No. 1)
Periodic output of N-CH OPEN DRAIN type or interrupt signal output of N-CH OPEN
DRAIN type for the CPU. The periodic output is used to check the reference signal and
oscillation frequency.
This pin is set as periodic output or interrupt signal output by writing “1” or “0” to the INT/
STND bit.
This output is not inhibited by CE. For more information, see “FUNCTIONAL DESCRIP-
TION OF REGISTERS”.
• DATA I/O (Pin No.2)
Input/output pin for setting of WRITE mode or READ mode, writing of addresses, or
writing/reading of data.
This pin is used as an input or output pin in high impedance state depending on whether
WRITE mode or READ mode is selected in the first 8-bit data cycle after the rising of the CE
input pulse.
• CLK (Pin No. 3)
Shift clock input pin. Data is taken in on the rising edge of a shift clock pulse when in WRITE
mode and data is output when in READ mode.
• CE (Pin No. 4)
Chip enable input pin. “H” level on this pin means “enable”.
When this pin is low, the DATA I/O pin goes into high impedance state, and DATA I/O and
CLK are disabled inside the LSI and current stops flowing through those pins.
“L” level on this pin forces the TEST and REST bits of the CF registers and the fr flag to be set
to “0”.
When turning the power ON, set this pin to “L” level.
• XT, XT (Pin Nos. 7 and 6)
32.768kHz crystal is to be connected to these pins.
C1
VDD
C2
XT
XT
MSM6782-01
XT
When an external clock is used, it is to be input from XT, while XT should be left open.
The oscillation crystal and capacitors should be placed as close to the IC as possible.
The oscillation circuit and other signal lines on any side of the LSI should be distant from each
other.
• VDD, VSS (Pin No.5)
Power supply pins. VDD is used for positive supply and VSS is for negative supply.
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