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CS61881-IB

Octal E1 Analog Front End

Cirrus Logic 

CS61881

For added flexibility the receive polarity select pin

(RPS) is provided to define whether RPOS/RNEG

have active high or low polarity. In addition, a re-

ceiver power down pin (RPD) is provided that

powers down all receivers and places RPOS,

RNEG, and RCLK into a high impedance state. Fi-

nally, to support applications that employ external

clock recovery, signals on RPOS and RNEG are

XORed and output on RCLK.

2.3 Loss-of-Signal Detector

Each receiver in the CS61881 has an analog loss-

of-signal (LOS) detector for ITU-G.775. An analog

LOS condition will be signaled on ALOS when the

input signal is less than 200 mV for 30 µS (Typ).

The LOS condition is cleared once the signal am-

plitude exceeds 250 mV. The ALOS signal will oc-

cur between 10 and 255 bits as specified by ITU

G.775.

Notes: During LOS the RPOS/RNEG outputs will be

active.

2.4 Loopback

The CS61881 provides two loopback modes for

each port. The LOOP pins are used to activate or

disable each port’s loopback operation. When the

LOOP pins are left open, loopback operation is dis-

abled. When a LOOP pin is tied either High or

Low, Local or Remote loopback is enabled respec-

tively.

2.4.1 Local Loopback

Local loopback is selected by driving LOOP High.

In this mode the data being transmitted on

TTIP/TRING is internally connected to the receiv-

er, and the RTIP/RRING inputs are disconnected.

2.4.2 Remote Loopback

Remote Loopback is selected by driving LOOP

Low. In remote loopback, the RPOS/RNEG and

RCLK outputs are internally input to the transmit

circuits for output on TTIP/TRING. In this mode

the TCLK, TPOS, and TNEG inputs are ignored.

2.5 5V Logic Support

The CS61881 provides digital interface pins capa-

ble of interfacing with 5 V logic. The overall power

consumption will still be minimized because the

IC’s core circuitry is powered by 3.3 V supplies.

2.6 JTAG Support

The CS61881 supports the IEEE Boundary Scan

Specification as described in the IEEE 1149.1 stan-

dards. A Test Access Port (TAP) is provided that

consists of the TAP controller, the boundary scan

register (BSR), and the 5 standard pins (TRSTB,

TCK, TMS, TDI, and TDO). A block diagram of

the test access port is shown in Figure 5. The test

clock input (TCK) is used to sample input data on

TDI, and shift output data through TDO. The TMS

input is used to step the TAP controller through its

various states.

The Test Access Port consists of the Tap Control-

ler, Instruction Register, by-pass register, device

ID register, and boundary scan register. The TMS

input is used to manipulate the TAP controller to

allow loading of the instruction and data registers.

The instruction register is used to select test execu-

tion or register access. The by-pass register pro-

vides a direct connection between the TDI input

and the TDO output. The device identification reg-

ister contains an n-bit device identifier.

The Boundary Scan Register is used to support test-

ing of IC inter-connectivity. Using the Boundary

Scan Register, the digital input pins can be sampled

and shifted out on TDO. In addition, this register

can also be used to drive digital output pins to a

user defined state.

2.6.1 TAP Controller

The TAP Controller is a 16 state synchronous state

machine clocked by the rising edge of TCK. The

TMS input governs state transitions as shown in

Figure 6. The value shown next to each state tran-

sition in the diagram is the value that must be on

TMS when it is sampled by the rising edge of TCK.

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DS451PP3

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