GENERAL DESCRIPTION
The XRT84V24 Quad E1 Framer IC contains four independent E1 Framer blocks. Each E1 Framer block contains its own Transmit and Receive E1 Framin function, Transmit HDLC Controller (which encapsulates contents of Transmit HDLC Buffers into LAPD Message frames) and Receiver HDLC Controller (which extracts payload content of “Receive LAPD Message” frames from the incoming E1 data stream and writes it into the Receive HDLC Buffer).

FEATURES
• Four independent, ITU-T G.704 compliant Transceiver E1 Framers
• Supports Channel Associated Signalin
• Supports Common-Channel and Primary Rate ISDN Signalin
• Supports FAS, CRC-Multiframe and CAS Multiframe framing stuctures
• Contains two 96 byte Transmit HDLC Buffers and two 96 byte Receive HDLC buffers for each channel
• Contains Microprocessor Interface for popular types of Microprocessors and supports Programmed I/O, Burst and DMA modes of Read/Write access
• Each framer block can encode or decode the E Frame data into/from the Single-Rail or Dual-Rail (AMI or HDB3 encoded) formats
• Detects and forces RAI and AIS Alarms
• Detects LOF, COFA and LOS conditions
• Each Framer Contains a 512 bit Elastic Store Buffer
• Uses a Single +3.3V Power Supply
• Available in either a 160 pin PQFP and 208 pin PQFP package

APPLICATIONS
• SDH terminal or add/drop multiplexers supporting E1 framing
• E1 multiplexers
• Channel Service Units (CSUs)
• LAN routers with integrated E1 interfaces
• E1 Frame Relay Interface
• ISDN Primary Rate Interfaces
• Test Equipment