DESCRIPTION
   The TH50VSF3680/3681AASB is a mixed multi-chip package containing a 8,388,608-bit Full CMOS SRAM and a 67,108,864-bit flash memory. The CIOS and CIOF inputs can be used to select the optimal memory configuration. The power supply. FLASH MEMORY a Simultaneous Read/Write operation so that data can be read during a Write or Erase operation. The TH50VSF3680/3681AASB can range from 2.7 V to 3.3 V. The TH50VSF3680/3681AASB is available in a 69-pin BGA package, making it suitable for a variety of design applications.

FEATURES
• Power supply voltage
   VCCs = 2.7 V~3.3 V
   VCCf = 2.7 V~3.3 V
• Data retention supply voltage
   VCCs = 1.5 V~3.3 V
• Current consumption
   Operating: 45 mA maximum (CMOS level)
   Standby: 10 µA maximum (SRAM CMOS level)
   Standby: 10 µA maximum (FLASH)
• Block erase architecture for flash memory
   8 × 8 Kbytes
   63 × 64 Kbytes
• Function mode control for flash memory
   Compatible with JEDEC-standard commands
• Flash memory functions
   Simultaneous Read/Write operations
   Auto-Program
   Auto Chip Erase, Auto Block Erase
   Auto Multiple-Block Erase
   Program Suspend/Resume
   Block-Erase Suspend/Resume
   Data Polling/Toggle Bit function
   Block Protection/Boot Block Protection
   Automatic Sleep, Hidden ROM Area Supports
   Common Flash Memory Interface (CFI)
   Byte/Word Mode
• Erase and Program cycle for flash memory
   105 cycles (typical)
• Boot block architecture for flash memory
   TH50VSF3680AASB: Top boot block
   TH50VSF3681AASB: Bottom boot block
• Package
   P-FBGA69-1209-0.80A3: 0.31 g (typ.)