50-MHz 32-bit RX MCUs, 78 DMIPS, up to 1-MB flash memory,
12-bit A/D, 10-bit D/A, ELC, MPC, RTC, up to 15 comms channels;
incorporating functions for IEC60730 compliance

FEATUREs
◾ 32-bit RX CPU core
   • Max. operating frequency: 50 MHz
      Capable of 78 DMIPS in operation at 50 MHz
   • Accumulator handles 64-bit results (for a single instruction)
      from 32- × 32-bit operations
   • Multiplication and division unit handles 32- × 32-bit
      operations (multiplication instructions take one CPU clock
      cycle)
   • Fast interrupt
   • CISC Harvard architecture with 5-stage pipeline
   • Variable-length instructions, ultra-compact code
   • On-chip debugging circuit
◾ Low power design and architecture
   • Operation from a single 1.62-V to 5.5-V supply
   • 1.62-V operation available (at up to 20 MHz)
   • Deep software standby mode with RTC remaining usable
   • Four low power consumption modes
◾ On-chip flash memory for code, no wait states
   • 50-MHz operation, 20-ns read cycle
   • No wait states for reading at full CPU speed
   • 64-K to 1-Mbyte capacities
   • User code programmable via the SCI
   • Programmable at 1.62 V
   • For instructions and operands
◾ On-chip data flash memory
   • 8 Kbytes
      (Number of times of reprogramming: 100,000)
   • Erasing and programming impose no load on the CPU.
◾ On-chip SRAM, no wait states
   • 12-K to 96-Kbyte size capacities
◾ DMA
   • DMAC: Incorporates four channels
   • DTC: Four transfer modes
◾ ELC
   • Module operation can be initiated by event signals without
      going through interrupts.
   • Modules can operate while the CPU is sleeping.
◾ Reset and supply management
   • Nine types of reset, including the power-on reset (POR)
   • Low voltage detection (LVD) with voltage settings
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