Product Description
PI6CV857L PLL clock device is developed for registered DDR DIMM applications This PLL Clock Buffer is designed for 2.5 VDDQand 2.5V AVDD operation and differential data input and output levels. Package options include plastic Thin Shrink Small-Outline Package (TSSOP).

Product Features
• PLL clock distribution optimized for Double Data Rate SDRAM applications.
• Distributes one differential clock input pair to ten differential clock output pairs.
• Inputs (CLK,CLK) and (FBIN,FBIN): SSTL_2
• Input PWRDWN: LVCMOS
• Outputs (Yx, Yx), (FBOUT, FBOUT): SSTL_2
• External feedback pins (FBIN,FBIN) are used to synchronize the outputs to the clock input.
• Operates at AVDD = 2.5V for core circuit and internal PLL, and VDDQ = 2.5V for differential output drivers
• Available Packages: Plastic 48-pin TSSOP