GENERAL DESCRIPTION
MX29LV161DT/B is a 16Mbit flash memory that can be organized as 1,048,576 words. These devices operate over a voltage range of 2.7V to 3.6V typically using a 3V power supply input. The memory array is divided into 32 equal 64 Kilo byte blocks. However, depending on the device being used as a Top-Boot or Bottom-Boot device. The outermost two sectors at the top or at the bottom are respectively the boot blocks for this device.

FEATURES
GENERAL FEATURES
• Word mode only
    - 1,048,576 x 16
• Sector Structure
    - 8K-Word x 1, 4K-Word x 2, 16K-Word x 1, 32K-Word x 31
    - Provides sector protect function to prevent program or erase operation in the protected sector
    - Provides chip unprotect function to allow code changing
    - Provides temporary sector unprotect function for code changing in previously protected sector
• Power Supply Operation
    - VCC 2.7 to 3.6 volt for read, erase, and program operations
    - VI/O 1.65V to 3.6V for Input/Output
• Latch-up protected to 100mA from -1V to 1.5xVcc
• Low Vcc write inhibit : Vcc ≤ Vlko
• Compatible with JEDEC standard
    - Pinout and software compatible to single power supply Flash

PERFORMANCE
• High Performance
    - Fast access time: 90ns
    - Word program time: 11us/word (typical)
    - Fast erase time: 0.7s/sector, 15s/chip (typical)
• Low Power Consumption
    - Low active read current: 5mA (typical) at 5MHz
    - Low standby current: 5uA (typical)
• 100,000 erase/program cycle (typical)
• 20 years data retention

SOFTWARE FEATURES
• Erase Suspend/ Erase Resume
    - Suspends sector erase operation to read data from or program data to another sector which is not being erased
• Status Reply
    - Data# Polling & Toggle bits provide detection of program and erase operation completion
• Support Common Flash Interface (CFI)

HARDWARE FEATURES
• Ready/Busy# (RY/BY#) Output
    - Provides a hardware method of detecting program and erase operation completion
• Hardware Reset (RESET#) Input
    - Provides a hardware method to reset the internal state machine to read mode
• WP#/ACC
    - Provide accelerated program capability

PACKAGE
• 48-Pin TSOP
• 48-Ball CSP (TFBGA)
• 48-Ball WFBGA/XFLGA
• All Pb-free devices are RoHS Compliant