64K x 18 Bit BurstRAM Synchronous Fast Static RAM
With Burst Counter and Registered Outputs

The MCM67J618A is a 1,179,648 bit synchronous static random access memory designed to provide a burstable, high–performance, secondary cache for the i486 and Pentium microprocessors. It is organized as 65,536 words of 18 bits, fabricated with Motorola’s high–performance silicon–gate BiCMOS technology. The device integrates input registers, a 2–bit counter, high speed SRAM, and high drive registered output drivers onto a single monolithic circuit for reduced parts count implementation of cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K). BiCMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability.

• Single 5 V ± 5% Power Supply
• Fast Access Time/Fast Cycle Time = 5 ns/100 MHz, 7 ns/80 MHz
• Byte Writeable via Dual Write Enables
• Internal Input Registers (Address, Data, Control)
• Output Registers for Pipelined Applications
• Internally Self–Timed Write Cycle
• ADSP, ADSC, and ADV Burst Control Pins
• Asynchronous Output Enable Controlled Three–State Outputs
• Common Data Inputs and Data Outputs
• 3.3 V I/O Compatible
• High Board Density 52–Lead PLCC Package
• ADSP Disabled with Chip Enable (E) – Supports Address Pipelining