The MCM63P531 is a 1M bit synchronous fast static RAM designed to provide a burstable, high performance, secondary cache for the 68K Family, PowerPC™, and Pentium™ microprocessors. It is organized as 32K words of 32 bits each, fabricated using high performance silicon gate CMOS technology. This device integrates input registers, an output register, a 2–bit address counter, and high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K). CMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability.

The MCM63P531 operates from a 3.3 V power supply, all inputs and outputs are LVTTL compatible.
• MCM63P531–4.5 = 4.5 ns access / 10 ns cycle
    MCM63P531–7 = 7 ns access / 13.3 ns cycle
    MCM63P531–8 = 8 ns access / 15 ns cycle
    MCM63P531–9 = 9 ns access / 16.6 ns cycle
• Single 3.3 V + 10%, – 5% Power Supply
• ADSP, ADSC, and ADV Burst Control Pins
• Selectable Burst Sequencing Order (Linear/Interleaved)
• Internally Self–Timed Write Cycle
• Byte Write and Global Write Control
• Sleep Mode (ZZ)
• Intel PBSRAM 2.0 Compliant
• Single–Cycle Deselect Timing
• 100 Pin TQFP Package