Quad 3-State D Flip-Flop with Common Clock and Reset
High–Performance Silicon–Gate CMOS

The MC74HC173 is identical in pinout to the LS173. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.
Data, when enabled, are clocked into the four D flip–flops with the rising edge of the common Clock. When either or both of the Output Enable Controls is high, the outputs are in a high–impedance state. This feature allows the HC173 to be used in bus–oriented systems. The Reset feature is asynchronous and active high.

• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard No. 7A
• Chip Complexity 208 FETs or 52 Equivalent Gates