The superscalar M68060 represents a new line of Motorola microprocessor products. The first generation of the M68060 product line consists of the MC68060, MC68LC060, and MC68EC060. All three microprocessors offer superscalar integer performance of over 100 MIPS at 66 MHz. The MC68060 comes fully equipped with both a floating-point unit (FPU) and a memory management unit (MMU) for high-performance embedded control and desktop applications. For cost-sensitive embedded control and desktop applications where an MMU is required, but the additional cost of a FPU is not justified, the MC68LC060 offers high performance at a low cost. Specifically designed for low-cost embedded control applications, the MC68EC060 eliminates both the FPU and MMU, permitting designers to leverage MC68060 performance while avoiding the cost of unnecessary features. Throughout this product brief, all references to the MC68060 also refer to the MC68LC060 and the MC68EC060, unless otherwise noted. Figure 1 illustrates a block diagram of the MC68060.

The following is a list of primary featuresof the MC68060:
• Fully User-Code Compatible with MC68040
• Superscalar Implementation of M68000 Architecture
   — Dual Integer Instruction Execution Improves Performance
• Branch Cache Reduces Branches to Zero Cycles
• Executes Three Instructions per Clock
• Dual 8-Kbyte On-Chip Caches
   — Separate Data and Instruction Caches
   — Simultaneous Access
   — Data Cache is Four-Way Banked to Allow Read and Write Access on Each Clock
• Bus Snooping
• Independent Instruction and Data Paged MMUs (MC68060 and MC68LC060 Only)
• Full 32-Bit Nonmultiplexed Address and Data Bus
   — Optimized to Achieve Very High Performance Using 32-Bit Memory System
   — Can Operate Bus at 1/2-or 1/4-Speed of Internal Clock
   — 32-Bit Bus Maximizes Data Throughput
   — Nonmultiplexed Bus Simplifies Design
   — Four-Deep Store Buffer and One-Deep Push Buffer to Maximize Write Bandwidth
   — MC68040-Compatible Bus Provides Simple Hardware Migration Path
• Power Management
   — Automatic Power-Down of Unused Blocks of Logic on a Clock-by-Clock Basis
   — Low-Voltage Operation at 3.3 V, with 3.3-V and 5-V I/O Capability
   — LPSTOP Mode Provides an Idle State for Lowest Standby Current
   — Static CMOS Technology Reduces Power in Normal Operation
• IEEE-Compatible On-Chip FPU (MC68060 Only)
• Available in 40-MHz (MC68EC060 only), 50-MHz, and 66-MHz Speeds
• Packaging
   — Ceramic Pin Grid Array (PGA)
   — Ceramic Quad Flat Pack (CQFP) (THIS PACKAGE NOT AVAILABLE 3/25/98)