These devices consist of bus transceiver circuits with 3-state D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to a high logic level.

• Independent Registers for A and B
• Multiplexed Real-Time and Stored Data
• Choice of True (F646) and Inverting (F648) Data Paths
• 3-State Outputs